MT41J128M16JT-125K Datasheet, PDF (157/211 Pages) Micron Technology – DDR3 SDRAM MT41J512M4 64 Meg x 4 x 8 Banks MT41J256M8 32 Meg x 8 x 8 Banks MT41J128M16 16 Meg x 16 x 8 Banks

2Gb: x4, x8, x16 DDR3 SDRAM
READ Operation
Figure 69 (page 159). DDR3 SDRAM does not allow interrupting or truncating any
READ burst.
Data from any READ burst must be completed before a subsequent WRITE burst is al-
lowed. An example of a READ burst followed by a WRITE burst for BL8 is shown in Fig-
ure 70 (page 159) (BC4 is shown in Figure 71 (page 160)). To ensure the READ data is
completed before the WRITE data is on the bus, the minimum READ-to-WRITE timing
is RL + ^tCCD - WL + 2^tCK.
A READ burst may be followed by a PRECHARGE command to the same bank, provided
auto precharge is not activated. The minimum READ-to-PRECHARGE command spac-
ing to the same bank is four clocks and must also satisfy a minimum analog time from
the READ command. This time is called ^tRTP (READ-to-PRECHARGE). ^tRTP starts AL
cycles later than the READ command. Examples for BL8 are shown in Figure 72
(page 160) and BC4 in Figure 73 (page 161). Following the PRECHARGE command, a
subsequent command to the same bank cannot be issued until ^tRP is met. The PRE-
CHARGE command followed by another PRECHARGE command to the same bank is al-
lowed. However, the precharge period will be determined by the last PRECHARGE com-
mand issued to the bank.
If A10 is HIGH when a READ command is issued, the READ with auto precharge func-
tion is engaged. The DRAM starts an auto precharge operation on the rising edge, which
is AL + ^tRTP cycles after the READ command. DRAM support a ^tRAS lockout feature (see
Figure 75 (page 161)). If ^tRAS (MIN) is not satisfied at the edge, the starting point of the
auto precharge operation will be delayed until ^tRAS (MIN) is satisfied. If ^tRTP (MIN) is
not satisfied at the edge, the starting point of the auto precharge operation is delayed
until ^tRTP (MIN) is satisfied. In case the internal precharge is pushed out by ^tRTP, ^tRP
starts at the point at which the internal precharge happens (not at the next rising clock
edge after this event). The time from READ with auto precharge to the next ACTIVATE
command to the same bank is AL + (^tRTP + ^tRP)*, where * means rounded up to the next
integer. In any event, internal precharge does not start earlier than four clocks after the
last 8n-bit prefetch.
PDF: 09005aef826aaadc
2Gb_DDR3_SDRAM.pdf - Rev. Q 04/13 EN
157
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