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| MT41J128M16JT-125K Datasheet, PDF (103/211 Pages) Micron Technology – DDR3 SDRAM MT41J512M4 64 Meg x 4 x 8 Banks MT41J256M8 32 Meg x 8 x 8 Banks MT41J128M16 16 Meg x 16 x 8 Banks | |||
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2Gb: x4, x8, x16 DDR3 SDRAM
Command and Address Setup, Hold, and Derating
Figure 35: Tangent Line for tIH (Command and Address â Clock)
tIS
tIH
CK
tIS
tIH
CK#
DQS#
DQS
VDDQ
VIH(AC)min
VIH(DC)min
DC to VREF
region
VREF(DC)
DC to VREF
region
VIL( DC)max
Tangen t
line
Nominal
line
Tangen t
line
Nominal
line
VIL( AC)max
VSS
ǻTR
ǻTR
Hold slew rate Tangent line (VREF(DC) - VIL(DC)max)
rising signal =
ǻTR
Hold slew rate Tangent line (VIH(DC)min - VREF(DC))
falling signal =
ǻTF
Note: 1. The clock and the strobe are drawn on different time scales.
PDF: 09005aef826aaadc
2Gb_DDR3_SDRAM.pdf - Rev. Q 04/13 EN
103
Micron Technology, Inc. reserves the right to change products or specifications without notice.
 2006 Micron Technology, Inc. All rights reserved.
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