MT41J128M16JT-125K Datasheet, PDF (121/211 Pages) Micron Technology – DDR3 SDRAM MT41J512M4 64 Meg x 4 x 8 Banks MT41J256M8 32 Meg x 8 x 8 Banks MT41J128M16 16 Meg x 16 x 8 Banks

2Gb: x4, x8, x16 DDR3 SDRAM
Commands
Figure 41: DLL Enable Mode to DLL Disable Mode
T0
CK#
CK
CKE
T1
Ta0
Ta1
Tb0
Tc0
Td0
Td1
Te0
Te1
Tf0
Valid1
Command _MRS²
6
NOP
t_MOD
ODT⁹
SRE³
NOP
t_CKSRE
7
t_CKESR
SRX⁴
t_CKSRX8
NOP
t_XS
MRS⁵
NOP
t_MOD
Valid¹
Valid¹
Indicates break
in time scale
Don’t Care
Notes:
1. Any valid command.
2. Disable DLL by setting MR1[0] to 1.
3. Enter SELF REFRESH.
4. Exit SELF REFRESH.
5. Update the mode registers with the DLL disable parameters setting.
6. Starting with the idle state, R_TT is in the High-Z state.
7. Change frequency.
8. Clock must be stable ^tCKSRX.
9. Static LOW in the case that R_TT,nom or R_TT(WR) is enabled; otherwise, static LOW or HIGH.
A similar procedure is required for switching from the DLL disable mode back to the
DLL enable mode. This also requires changing the frequency during self refresh mode
(see Figure 42 (page 122)).
1. Starting from the idle state (all banks are precharged, all timings are fulfilled, ODT
is turned off, and R_TT,nom and R_TT(WR) are High-Z), enter self refresh mode.
2. After ^tCKSRE is satisfied, change the frequency to the new clock rate.
3. Self refresh may be exited when the clock is stable with the new frequency for
t_{CKSRX. After} t_{XS is satisfied, update the mode registers with the appropriate val-}
ues. At a minimum, set MR1[0] to 0 to enable the DLL. Wait ^tMRD, then set MR0[8]
to 1 to enable DLL RESET.
4. After another ^tMRD delay is satisfied, update the remaining mode registers with
the appropriate values.
5. The DRAM will be ready for its next command in the DLL enable mode after the
greater of ^tMRD or ^tMOD has been satisfied. However, before applying any com-
mand or function requiring a locked DLL, a delay of ^tDLLK after DLL RESET must
be satisfied. A ZQCL command should be issued with the appropriate timings met.
PDF: 09005aef826aaadc
2Gb_DDR3_SDRAM.pdf - Rev. Q 04/13 EN
121
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