MT41J128M16JT-125K Datasheet, PDF (169/211 Pages) Micron Technology – DDR3 SDRAM MT41J512M4 64 Meg x 4 x 8 Banks MT41J256M8 32 Meg x 8 x 8 Banks MT41J128M16 16 Meg x 16 x 8 Banks

2Gb: x4, x8, x16 DDR3 SDRAM
WRITE Operation
Figure 83: WRITE Burst
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
CK#
CK
Command¹
WRITE
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
WL = AL + CWL
Address²
Bank,
Col n
DQS, DQS#
t_{DQSS (MIN)}
t_WPRE ^tDQSS ^tDSH
t_DSH
t_DSH
t_DSH t_WPST
t_DQSH t_DQSL t_DQSH t_DQSL t_DQSH t_DQSL t_DQSH t_DQSL t_DQSH t_DQSL
DQ³
DI
DI
DI
DI
DI
DI
DI
DI
n
n+1 n+2 n+3 n+4 n+5 n+6 n+7
DQS, DQS#
t_{DQSS (NOM)}
DQ³
DQS, DQS#
t_{DQSS (MAX)}
DQ³
t_WPRE
t_DSH
t_DSH
t_DSH
t_DSH t_WPST
t_DQSH
t_DQSL
t_DSS
t_DQSH
t_DQSL
t_DSS
t_DQSH
t_DQSL
t_DSS
t_DQSH
t_DQSL t_DQSH
t_DSS
t_DQSL
t_DSS
DI
DI
DI
DI
DI
DI
DI
DI
n
n+1 n+2 n+3 n+4 n+5 n+6 n+7
t_DQSS
t_WPRE
t_WPST
t_DQSH t_DQSL t_DQSH t_DQSL t_DQSH t_DQSL t_DQSH t_DQSL t_DQSH t_DQSL
t_DSS
t_DSS
t_DSS
t_DSS
t_DSS
DI
DI
DI
DI
DI
DI
DI
DI
n
n+1 n+2 n+3 n+4 n+5 n+6 n+7
Transitioning Data
Don’t Care
Notes:
1. NOP commands are shown for ease of illustration; other commands may be valid at
these times.
2. The BL8 setting is activated by either MR0[1:0] = 00 or MR0[1:0] = 01 and A12 = 1 during
the WRITE command at T0.
3. DI n = data-in for column n.
4. BL8, WL = 5 (AL = 0, CWL = 5).
5. ^tDQSS must be met at each rising clock edge.
6. ^tWPST is usually depicted as ending at the crossing of DQS, DQS#; however, ^tWPST ac-
tually ends when DQS no longer drives LOW and DQS# no longer drives HIGH.
PDF: 09005aef826aaadc
2Gb_DDR3_SDRAM.pdf - Rev. Q 04/13 EN
169
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