MT41J128M16JT-125K Datasheet, PDF (159/211 Pages) Micron Technology – DDR3 SDRAM MT41J512M4 64 Meg x 4 x 8 Banks MT41J256M8 32 Meg x 8 x 8 Banks MT41J128M16 16 Meg x 16 x 8 Banks

Figure 69: Nonconsecutive READ Bursts
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
CK#
CK
Command
READ
NOP
NOP
NOP
NOP
READ
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
Address
Bank a,
Col n
Bank a,
Col b
DQS, DQS#
DQ
CL = 8
CL = 8
DO
DO
n
b
Notes:
1. AL = 0, RL = 8.
2. DO n (or b) = data-out from column n (or column b).
3. Seven subsequent elements of data-out appear in the programmed order following DO n.
4. Seven subsequent elements of data-out appear in the programmed order following DO b.
Transitioning Data
Don’t Care
Figure 70: READ (BL8) to WRITE (BL8)
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
CK#
CK
Command¹
READ
Address²
Bank,
Col n
DQS, DQS#
DQ3
NOP
NOP
NOP
NOP
NOP
READ-to-WRITE command delay = RL + ^tCCD + 2^tCK - WL
t_RPRE
WRITE
NOP
Bank,
Col b
NOP
NOP
t_RPST
RL = 5
DO DO DO DO DO DO DO DO
n n+1 n+2 n+3 n+4 n+5 n+6 n+7
WL = 5
NOP
NOP
NOP
NOP
NOP
NOP
t_{BL = 4 clocks}
t_WR
t_WR
t_WPRE
t_WPST
DI
DI
DI DI
DI
DI
DI
DI
n n+1 n+2 n+3 n+4 n+5 n+6 n+7
Transitioning Data
Don’t Care
Notes:
1. NOP commands are shown for ease of illustration; other commands may be valid at these times.
2. The BL8 setting is activated by either MR0[1:0] = 00 or MR0[1:0] = 01 and A12 = 1 during the READ command at
T0, and the WRITE command at T6.
3. DO n = data-out from column, DI b = data-in for column b.
4. BL8, RL = 5 (AL = 0, CL = 5), WL = 5 (AL = 0, CWL = 5).