MT41J128M16JT-125K Datasheet, PDF(189/211 Page) Micron Technology – DDR3 SDRAM MT41J512M4 64 Meg x 4 x 8 Banks MT41J256M8 32 Meg x 8 x 8 Banks MT41J128M16 16 Meg x 16 x 8 Banks

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MT41J128M16JT-125K Datasheet, PDF (189/211 Pages) Micron Technology – DDR3 SDRAM MT41J512M4 64 Meg x 4 x 8 Banks MT41J256M8 32 Meg x 8 x 8 Banks MT41J128M16 16 Meg x 16 x 8 Banks

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2Gb: x4, x8, x16 DDR3 SDRAM

RESET Operation

Figure 106: RESET Sequence

System RESET

(warm boot)

Stable and

valid clock T0

T1

tCK

CK#

CK

T = 100ns (MIN)

tCL

tCL

t CKSRX1

RESET# tIOZ = 20ns

tIS

T = 10ns (MIN)

Ta0

Tb0

Tc0

CKE

tIS

ODT

Static LOW in case RTT_Nom is enabled at time Ta0, otherwise static HIGH or LOW

tIS

Command

NOP

MRS

MRS

MRS

MRS

ZQCL

DM

Td0

Valid

tIS

Valid

Valid

Address

Code

Code

Code

Code

Valid

A10

BA[2:0]

DQS

DQ

RTT

All voltage

supplies valid

and stable

Code

Code

Code

Code

A10 = H

Valid

High-Z

High-Z

High-Z

T = 500Î¼s (MIN)

BA0 = L

BA1 = H

BA2 = L

BA0 = H

BA1 = H

BA2 = L

BA0 = H

BA1 = L

BA2 = L

BA0 = L

BA1 = L

BA2 = L

tXPR

tMRD

tMRD

tMRD

tMOD

Valid

MR2

DRAM ready

for external

commands

MR3

MR1 with

DLL ENABLE

MR0 with

DLL RESET

ZQCAL

tZQinit

tDLLK

Normal

operation

Indicates break

in time scale

Donât Care

Note: 1. The minimum time required is the longer of 10ns or 5 clocks.

PDF: 09005aef826aaadc

2Gb_DDR3_SDRAM.pdf - Rev. Q 04/13 EN

189

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