PIC18F25K20T-ISS Datasheet, PDF (81/456 Pages) Microchip Technology – 28/40/44-Pin Flash Microcontrollers with nanoWatt XLP Technology

PIC18F2XK20/4XK20
TABLE 5-2: REGISTER FILE SUMMARY (PIC18F2XK20/4XK20) (CONTINUED)
File Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on Details
POR, BOR on page:
SPBRGH EUSART Baud Rate Generator Register, High Byte
0000 0000 61, 241
SPBRG
EUSART Baud Rate Generator Register, Low Byte
0000 0000 61, 241
RCREG
EUSART Receive Register
0000 0000 61, 238
TXREG
EUSART Transmit Register
0000 0000 61, 237
TXSTA
CSRC
TX9
TXEN
SYNC
SENDB
BRGH
TRMT
TX9D 0000 0010 61, 246
RCSTA
SPEN
RX9
SREN
CREN
ADDEN
FERR
OERR
RX9D 0000 000x 61, 247
EEADR
EEADRH⁽⁷⁾
EEADR7
—
EEADR6
—
EEADR5
—
EEADR4
—
EEADR3
—
EEADR2
—
EEADR1
EEADR9
EEADR0 0000 0000 61, 90, 99
EEADR8 ---- --00 61, 90, 99
EEDATA
EEPROM Data Register
0000 0000 61, 90, 99
EECON2 EEPROM Control Register 2 (not a physical register)
0000 0000 61, 90, 99
EECON1
EEPGD
CFGS
—
FREE
WRERR
WREN
WR
RD
xx-0 x000 61, 91, 99
IPR2
OSCFIP
C1IP
C2IP
EEIP
BCLIP
HLVDIP
TMR3IP
CCP2IP 1111 1111 62, 117
PIR2
OSCFIF
C1IF
C2IF
EEIF
BCLIF
HLVDIF
TMR3IF
CCP2IF 0000 0000 62, 113
PIE2
IPR1
PIR1
PIE1
OSCTUNE
TRISE⁽²⁾
TRISD⁽²⁾
OSCFIE
PSPIP⁽²⁾
PSPIF⁽²⁾
PSPIE⁽²⁾
INTSRC
C1IE
ADIP
ADIF
ADIE
PLLEN⁽³⁾
C2IE
RCIP
RCIF
RCIE
TUN5
IBF
OBF
IBOV
PORTD Data Direction Control Register
EEIE
TXIP
TXIF
TXIE
TUN4
PSPMODE
BCLIE
SSPIP
SSPIF
SSPIE
TUN3
—
HLVDIE
CCP1IP
CCP1IF
CCP1IE
TUN2
TRISE2
TMR3IE
TMR2IP
TMR2IF
TMR2IE
TUN1
TRISE1
CCP2IE
TMR1IP
TMR1IF
TMR1IE
TUN0
TRISE0
0000 0000
1111 1111
0000 0000
0000 0000
0q00 0000
0000 -111
1111 1111
62, 115
62, 116
62, 112
62, 114
33, 62
62, 134
62, 130
TRISC
PORTC Data Direction Control Register
1111 1111 62, 127
TRISB
TRISA
LATE⁽²⁾
LATD⁽²⁾
PORTB Data Direction Control Register
TRISA7⁽⁵⁾ TRISA6⁽⁵⁾ Data Direction Control Register for PORTA
—
—
—
—
—
PORTE Data Latch Register
(Read and Write to Data Latch)
PORTD Data Latch Register (Read and Write to Data Latch)
1111 1111
1111 1111
---- -xxx
62, 124
62, 121
62, 133
xxxx xxxx 62, 130
LATC
PORTC Data Latch Register (Read and Write to Data Latch)
xxxx xxxx 62, 127
LATB
LATA
PORTE
PORTD⁽²⁾
PORTB Data Latch Register (Read and Write to Data Latch)
LATA7⁽⁵⁾ LATA6⁽⁵⁾ PORTA Data Latch Register (Read and Write to Data Latch)
—
—
—
—
RE3⁽⁴⁾
RE2⁽²⁾
RE1⁽²⁾
RD7
RD6
RD5
RD4
RD3
RD2
RD1
RE0⁽²⁾
RD0
xxxx xxxx
xxxx xxxx
---- x000
xxxx xxxx
62, 124
62, 121
62, 133
62, 130
PORTC
RC7
RC6
RC5
RC4
RC3
RC2
RC1
RC0 xxxx xxxx 62, 127
PORTB
PORTA
ANSELH⁽⁶⁾
ANSEL
RB7
RA7⁽⁵⁾
—
ANS7⁽²⁾
RB6
RA6⁽⁵⁾
—
ANS6⁽²⁾
RB5
RA5
—
ANS5⁽²⁾
RB4
RA4
ANS12
ANS4
RB3
RA3
ANS11
ANS3
RB2
RA2
ANS10
ANS2
RB1
RA1
ANS9
ANS1
RB0
RA0
ANS8
ANS0
xxx0 0000
xx0x 0000
---1 1111
1111 1111
62, 124
62, 121
62, 137
62, 136
IOCB
IOCB7
IOCB6
IOCB5
IOCB4
—
—
—
—
0000 ---- 62, 124
WPUB
WPUB7
WPUB6
WPUB5
WPUB4
WPUB3
WPUB2
WPUB1
WPUB0 1111 1111 62, 124
CM1CON0
C1ON
C1OUT
C1OE
C1POL
C1SP
C1R
C1CH1
C1CH0 0000 0000 62, 284
CM2CON0
C2ON
C2OUT
C2OE
C2POL
C2SP
C2R
C2CH1
C2CH0 0000 0000 62, 285
CM2CON1
SLRCON
MC1OUT
—
MC2OUT
—
C1RSEL
—
C2RSEL
SLRE⁽²⁾
—
SLRD⁽²⁾
—
SLRC
—
SLRB
—
SLRA
0000 ---- 63, 287
---1 1111 63, 138
SSPMSK
MSK7
MSK6
MSK5
MSK4
MSK3
MSK2
MSK1
MSK0 1111 1111 63, 213
Legend:
Note 1:
2:
3:
4:
5:
6:
7:
x = unknown, u = unchanged, — = unimplemented, q = value depends on condition
The SBOREN bit is only available when the BOREN<1:0> Configuration bits = 01; otherwise it is disabled and reads as ‘0’. See
Section 4.4 “Brown-out Reset (BOR)”.
These registers and/or bits are not implemented on 28-pin devices and are read as ‘0’. Reset values are shown for 40/44-pin devices;
individual unimplemented bits should be interpreted as ‘-’.
The PLLEN bit is only available in specific oscillator configuration; otherwise it is disabled and reads as ‘0’. See Section 2.6.2 “PLL in
HFINTOSC Modes”.
The RE3 bit is only available when Master Clear Reset is disabled (MCLRE Configuration bit = 0). Otherwise, RE3 reads as ‘0’. This bit is
read-only.
RA6/RA7 and their associated latch and direction bits are individually configured as port pins based on various primary oscillator modes.
When disabled, these bits read as ‘0’.
All bits of the ANSELH register initialize to ‘0’ if the PBADEN bit of CONFIG3H is ‘0’.
This register is only implemented in the PIC18F46K20 and PIC18F26K20 devices.
 2010 Microchip Technology Inc.
DS41303G-page 81