PIC18F25K20T-ISS Datasheet, PDF (221/456 Pages) Microchip Technology – 28/40/44-Pin Flash Microcontrollers with nanoWatt XLP Technology

PIC18F2XK20/4XK20
17.4.7 BAUD RATE
In I²C Master mode, the Baud Rate Generator (BRG)
reload value is placed in the SSPADD register
(Figure 17-17). When a write occurs to SSPBUF, the
Baud Rate Generator will automatically begin counting.
The BRG counts down to ‘0’ and stops until another
reload has taken place. The BRG count is decre-
mented twice per instruction cycle (TCY) on the Q2 and
Q4 clocks. In I²C Master mode, the BRG is reloaded
automatically. One half of the SCL period is equal to
[(SSPADD+1)  2]/FOSC. Therefore SSPADD =
(FCY/FSCL) -1.
Once the given operation is complete (i.e.,
transmission of the last data bit is followed by ACK), the
internal clock will automatically stop counting and the
SCL pin will remain in its last state.
Table 17-3 demonstrates clock rates based on
instruction cycles and the BRG value loaded into
SSPADD.
The minimum SSPADD value for baud rate generation
is 0x03.
FIGURE 17-17: BAUD RATE GENERATOR BLOCK DIAGRAM
SSPM<3:0>
SSPADD<7:0>
SSPM<3:0>
SCL
Reload
Control
Reload
CLKOUT
BRG Down Counter
FOSC/2
TABLE 17-3: I²C™ CLOCK RATE W/BRG
FOSC
FCY
BRG Value
FSCL
(2 Rollovers of BRG)
64 MHz
16 MHz
27h
400 kHz⁽¹⁾
64 MHz
16 MHz
32h
313.7 kHz
64 MHz
40 MHz
16 MHz
10 MHz
3Fh
250 kHz
18h
400 kHz⁽¹⁾
40 MHz
10 MHz
1Fh
312.5 kHz
40 MHz
16 MHz
10 MHz
4 MHz
63h
100 kHz
09h
400 kHz⁽¹⁾
16 MHz
4 MHz
0Ch
308 kHz
16 MHz
4 MHz
27h
100 kHz
4 MHz
1 MHz
09h
100 kHz
Note 1: The I²C interface does not conform to the 400 kHz I²C specification (which applies to rates greater than
100 kHz) in all details, but may be used with care where higher rates are required by the application.
 2010 Microchip Technology Inc.
DS41303G-page 221