PIC18F25K20T-ISS Datasheet, PDF (268/456 Pages) Microchip Technology – 28/40/44-Pin Flash Microcontrollers with nanoWatt XLP Technology

PIC18F2XK20/4XK20
19.2 ADC Operation
19.2.1 STARTING A CONVERSION
To enable the ADC module, the ADON bit of the
ADCON0 register must be set to a ‘1’. Setting the GO/
DONE bit of the ADCON0 register to a ‘1’ will, depend-
ing on the ACQT bits of the ADCON2 register, either
immediately start the Analog-to-Digital conversion or
start an acquisition delay followed by the Analog-to-
Digital conversion.
Figure 19-3 shows the operation of the A/D converter
after the GO bit has been set and the ACQT<2:0> bits
are cleared. A conversion is started after the following
instruction to allow entry into SLEEP mode before the
conversion begins.
Figure 19-4 shows the operation of the A/D converter
after the GO bit has been set and the ACQT<2:0> bits
are set to ‘010’ which selects a 4 TAD acquisition time
before the conversion starts.
Note:
The GO/DONE bit should not be set in the
same instruction that turns on the ADC.
Refer to Section 19.2.9 “A/D Conver-
sion Procedure”.
FIGURE 19-3:
A/D CONVERSION TAD CYCLES (ACQT<2:0> = 000, TACQ = 0)
TCY - TAD TAD1 TAD2 TAD3 TAD4 TAD5 TAD6 TAD7 TAD8 TAD9 TAD10 TAD11 2 TAD
b9 b8 b7 b6 b5 b4 b3 b2 b1 b0
Conversion starts
Holding capacitor is disconnected from analog input (typically 100 ns)
Discharge
Set GO bit
On the following cycle:
ADRESH:ADRESL is loaded, GO bit is cleared,
ADIF bit is set, holding capacitor is connected to analog input.
FIGURE 19-4:
A/D CONVERSION TAD CYCLES (ACQT<2:0> = 010, TACQ = 4 TAD)
TACQT Cycles
TAD Cycles
1234123456789
Automatic
Acquisition
Time
b9 b8 b7 b6 b5 b4 b3 b2
Conversion starts
(Holding capacitor is disconnected from analog input)
10 11 2 TAD
b1 b0
Discharge
Set GO bit
(Holding capacitor continues
acquiring input)
On the following cycle:
ADRESH:ADRESL is loaded, GO bit is cleared,
ADIF bit is set, holding capacitor is connected to analog input.
DS41303G-page 268
 2010 Microchip Technology Inc.