PIC18F25K20T-ISS Datasheet, PDF (261/456 Pages) Microchip Technology – 28/40/44-Pin Flash Microcontrollers with nanoWatt XLP Technology

PIC18F2XK20/4XK20
FIGURE 18-12: SYNCHRONOUS RECEPTION (MASTER MODE, SREN)
RX/DT
pin
TX/CK pin
(SCKP = 0)
bit 0
bit 1
bit 2
bit 3
bit 4
bit 5
bit 6
bit 7
TX/CK pin
(SCKP = 1)
Write to
bit SREN
SREN bit
CREN bit ^{‘0’}
‘0’
RCIF bit
(Interrupt)
Read
RXREG
Note:
Timing diagram demonstrates Sync Master mode with bit SREN = 1 and bit BRGH = 0.
TABLE 18-8: REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER RECEPTION
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset
Values
on page
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF
59
PIR1
PSPIF⁽¹⁾ ADIF
RCIF
TXIF
SSPIF CCP1IF TMR2IF TMR1IF
62
PIE1
PSPIE⁽¹⁾ ADIE
RCIE
TXIE
SSPIE CCP1IE TMR2IE TMR1IE 62
IPR1
PSPIP⁽¹⁾ ADIP
RCIP
TXIP
SSPIP CCP1IP TMR2IP TMR1IP 62
RCSTA
SPEN
RX9
SREN CREN ADDEN FERR OERR RX9D
61
RCREG EUSART Receive Register
61
TXSTA
CSRC
TX9
TXEN SYNC SENDB BRGH TRMT TX9D
61
BAUDCON ABDOVF RCIDL DTRXP CKTXP BRG16
—
WUE ABDEN
61
SPBRGH EUSART Baud Rate Generator Register, High Byte
61
SPBRG EUSART Baud Rate Generator Register, Low Byte
61
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for synchronous master reception.
Note 1: Reserved in 28-pin devices; always maintain these bits clear.
 2010 Microchip Technology Inc.
DS41303G-page 261