PIC18F25K20T-ISS Datasheet, PDF (202/456 Pages) Microchip Technology – 28/40/44-Pin Flash Microcontrollers with nanoWatt XLP Technology

PIC18F2XK20/4XK20
17.4 I²C Mode
The MSSP module in I²C mode fully implements all
master and slave functions (including general call
support) and provides interrupts on Start and Stop bits
in hardware to determine a free bus (multi-master
function). The MSSP module implements the standard
mode specifications as well as 7-bit and 10-bit
addressing.
Two pins are used for data transfer:
• Serial clock (SCL) – SCK/SCL
• Serial data (SDA) – SDI/SDA
The user must configure these pins as inputs with the
corresponding TRIS bits.
FIGURE 17-7:
MSSP BLOCK DIAGRAM
(I²C™ MODE)
Read
Internal
Data Bus
Write
SCK/SCL
SDI/SDA
SSPBUF Reg
Shift
Clock
SSPSR Reg
MSb
LSb
SSPMSK Reg
Match Detect
Addr Match
SSPADD Reg
Start and
Stop bit Detect
Set, Reset
S, P bits
(SSPSTAT Reg)
17.4.1 REGISTERS
The MSSP module has seven registers for I²C
operation. These are:
• MSSP Control Register 1 (SSPCON1)
• MSSP Control Register 2 (SSPCON2)
• MSSP STATUS register (SSPSTAT)
• Serial Receive/Transmit Buffer Register
(SSPBUF)
• MSSP Shift Register (SSPSR) – Not directly
accessible
• MSSP Address Register (SSPADD)
• MSSP Address Mask (SSPMSK)
SSPCON1, SSPCON2 and SSPSTAT are the control
and STATUS registers in I²C mode operation. The
SSPCON1 and SSPCON2 registers are readable and
writable. The lower 6 bits of the SSPSTAT are read-only.
The upper two bits of the SSPSTAT are read/write.
SSPSR is the shift register used for shifting data in or
out. SSPBUF is the buffer register to which data bytes
are written to or read from.
When the SSP is configured in Master mode, the lower
seven bits of SSPADD act as the Baud Rate Generator
reload value. When the SSP is configured for I²C slave
mode the SSPADD register holds the slave device
address. The SSP can be configured to respond to a
range of addresses by qualifying selected bits of the
address register with the SSPMSK register.
In receive operations, SSPSR and SSPBUF together
create a double-buffered receiver. When SSPSR
receives a complete byte, it is transferred to SSPBUF
and the SSPIF interrupt is set.
During transmission, the SSPBUF is not
double-buffered. A write to SSPBUF will write to both
SSPBUF and SSPSR.
DS41303G-page 202
 2010 Microchip Technology Inc.