PIC18F25K20T-ISS Datasheet, PDF (49/456 Pages) Microchip Technology – 28/40/44-Pin Flash Microcontrollers with nanoWatt XLP Technology

PIC18F2XK20/4XK20
3.5.4
EXIT WITHOUT AN OSCILLATOR
START-UP DELAY
Certain exits from power-managed modes do not
invoke the OST at all. There are two cases:
• PRI_IDLE mode, where the primary clock source
is not stopped and
• the primary clock source is not any of the LP, XT,
HS or HSPLL modes.
In these instances, the primary clock source either
does not require an oscillator start-up delay since it is
already running (PRI_IDLE), or normally does not
require an oscillator start-up delay (RC, EC, INTOSC,
and INTOSCIO modes). However, a fixed delay of
interval TCSD following the wake event is still required
when leaving Sleep and Idle modes to allow the CPU
to prepare for execution. Instruction execution resumes
on the first clock cycle following this delay.
TABLE 3-3: EXIT DELAY ON WAKE-UP BY RESET FROM SLEEP MODE OR ANY IDLE MODE
(BY CLOCK SOURCES)
Clock Source
before Wake-up
Clock Source
after Wake-up
Exit Delay
Clock Ready Status
Bit (OSCCON)
LP, XT, HS
Primary Device Clock
(PRI_IDLE mode)
T1OSC or LFINTOSC⁽¹⁾
HFINTOSC⁽²⁾
None
(Sleep mode)
HSPLL
EC, RC
HFINTOSC⁽²⁾
LP, XT, HS
HSPLL
EC, RC
HFINTOSC⁽¹⁾
LP, XT, HS
HSPLL
EC, RC
HFINTOSC⁽¹⁾
LP, XT, HS
HSPLL
EC, RC
HFINTOSC⁽¹⁾
TCSD⁽¹⁾
TOST⁽³⁾
TOST + t_PLL⁽³⁾
TCSD⁽¹⁾
TIOBST⁽⁴⁾
TOST⁽⁴⁾
TOST + t_PLL⁽³⁾
TCSD⁽¹⁾
None
TOST⁽³⁾
TOST + t_PLL⁽³⁾
TCSD⁽¹⁾
TIOBST⁽⁴⁾
OSTS
IOFS
OSTS
IOFS
OSTS
IOFS
OSTS
IOFS
Note 1: TCSD (parameter 38) is a required delay when waking from Sleep and all Idle modes and runs concurrently
with any other required delays (see Section 3.4 “Idle Modes”). On Reset, HFINTOSC defaults to 1 MHz.
2: Includes both the HFINTOSC 16 MHz source and postscaler derived frequencies.
3: TOST is the Oscillator Start-up Timer (parameter 32). t_PLL is the PLL Lock-out Timer (parameter F12).
4: Execution continues during the HFINTOSC stabilization period, TIOBST (parameter 39).
 2010 Microchip Technology Inc.
DS41303G-page 49