PIC16F526 Datasheet, PDF (69/122 Pages) Microchip Technology – 14-Pin, 8-Bit Flash Microcontroller

PIC16F526
11.0 COMPARATOR VOLTAGE
REFERENCE MODULE
The Comparator Voltage Reference module also
allows the selection of an internally generated voltage
reference for one of the C2 comparator inputs. The
VRCON register (Register 11-1) controls the Voltage
Reference module shown in Figure 11-1.
11.1 Configuring The Voltage
Reference
The voltage reference can output 32 voltage levels; 16
in a high range and 16 in a low range.
Equation 11-1 determines the output voltages:
EQUATION 11-1:
VRR = 1 (low range): CVREF = (VR<3:0>/24) x VDD
VRR = 0 (high range):
CVREF = (VDD/4) + (VR<3:0> x VDD/32)
11.2 Voltage Reference Accuracy/Error
The full range of VSS to VDD cannot be realized due to
construction of the module. The transistors on the top
and bottom of the resistor ladder network (Figure 11-1)
keep CVREF from approaching VSS or VDD. The
exception is when the module is disabled by clearing
the VREN bit of the VRCON register. When disabled,
the reference voltage is VSS when VR<3:0> is ‘0000’
and the VRR bit of the VRCON register is set. This
allows the comparator to detect a zero-crossing and
not consume the CVREF module current.
The voltage reference is VDD derived and, therefore,
the CVREF output changes with fluctuations in VDD.
The tested absolute accuracy of the comparator
voltage reference can be found in Section 14.0 “Elec-
trical Characteristics”.
REGISTER 11-1: VRCON: VOLTAGE REFERENCE CONTROL REGISTER
R/W-0
R/W-0
R/W-0
U-0
R/W-0
R/W-0
VREN
VROE
VRR
—
VR3
VR2
bit 7
R/W-0
VR1
R/W-0
VR0
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
bit 6
bit 5
bit 4
bit 3-0
VREN: CVREF Enable bit
1 = CVREF is powered on
0 = CVREF is powered down, no current is drawn
VROE: CVREF Output Enable bit⁽¹⁾
1 = CVREF output is enabled
0 = CVREF output is disabled
VRR: CVREF Range Selection bit
1 = Low range
0 = High range
Unimplemented: Read as ‘0’
VR<3:0> CVREF Value Selection bit
When VRR = 1: CVREF= (VR<3:0>/24)*VDD
When VRR = 0: CVREF= VDD/4+(VR<3:0>/32)*VDD
Note 1: When this bit is set, the TRIS for the CVREF pin is overridden and the analog voltage is placed on the
CVREF pin.
 2010 Microchip Technology Inc.
DS41326D-page 69