PIC16F526 Datasheet, PDF (15/122 Pages) Microchip Technology – 14-Pin, 8-Bit Flash Microcontroller

4.0 MEMORY ORGANIZATION
The PIC16F526 memories are organized into program
memory and data memory (SRAM).The self-writable
portion of the program memory called Flash data
memory is located at addresses at 400h-43Fh. All
Program mode commands that work on the normal
Flash memory work on the Flash data memory. This
includes bulk erase, row/column/cycling toggles, Load
and Read data commands (Refer to Section 5.0
“Flash Data Memory Control” for more details). For
devices with more than 512 bytes of program memory,
a paging scheme is used. Program memory pages are
accessed using one STATUS register bit. For the
PIC16F526, with data memory register files of more
than 32 registers, a banking scheme is used. Data
memory banks are accessed using the File Select
Register (FSR).
4.1 Program Memory Organization for
the PIC16F526
The PIC16F526 device has an 11-bit Program Counter
(PC) capable of addressing a 2K x 12 program memory
space. Program memory is partitioned into user memory,
data memory and configuration memory spaces.
The user memory space is the on-chip user program
memory. As shown in Figure 4-1, it extends from 0x000
to 0x3FF and partitions into pages, including Reset
vector at address 0x3FF.
The data memory space is the Flash data memory
block and is located at addresses PC = 400h-43Fh. All
Program mode commands that work on the normal
Flash memory work on the Flash data memory block.
This includes bulk erase, Load and Read data
commands.
The configuration memory space extends from 0x440
to 0x7FF. Locations from 0x448 through 0x49F are
reserved. The user ID locations extend from 0x440
through 0x443. The Backup OSCCAL locations extend
from 0x444 through 0x447. The Configuration Word is
physically located at 0x7FF.
Refer to “PIC16F526 Memory Programming
Specification” (DS41317) for more details.
PIC16F526
FIGURE 4-1:
MEMORY MAP
On-chip User
Program
Memory (Page 0)
On-chip User
Program
Memory (Page 1)
Reset Vector
Flash Data Memory
User ID Locations
Backup OSCCAL
Locations
Reserved
Unimplemented
Configuration Word
000h
1FFh
200h
3FEh
3FFh
400h
43Fh
440h
443h
444h
447h
448h
49Fh
4A0h
7FEh
7FFh
 2010 Microchip Technology Inc.
DS41326D-page 15