PIC16F526 Datasheet, PDF (23/122 Pages) Microchip Technology – 14-Pin, 8-Bit Flash Microcontroller

5.0 FLASH DATA MEMORY
CONTROL
The Flash data memory is readable and writable during
normal operation (full VDD range). This memory is not
directly mapped in the register file space. Instead, it is
indirectly addressed through the Special Function
Registers (SFRs).
5.1 Reading Flash Data Memory
To read a Flash data memory location the user must:
• Write the EEADR register
• Set the RD bit of the EECON register
The value written to the EEADR register determines
which Flash data memory location is read. Setting the
RD bit of the EECON register initiates the read. Data
from the Flash data memory read is available in the
EEDATA register immediately. The EEDATA register
will hold this value until another read is initiated or it is
modified by a write operation. Program execution is
suspended while the read cycle is in progress.
Execution will continue with the instruction following the
one that sets the WR bit. See Example 1 for sample
code.
EXAMPLE 1: READING FROM FLASH
DATA MEMORY
BANKSEL EEADR
MOVF DATA_EE_ADDR, W
MOVWF EEADR
BANKSEL EECON1
;
;
;Data Memory
;Address to read
;
BSF EECON, RD
MOVF EEDATA, W
;EE Read
;W = EEDATA
Note: Only a BSF command will work to enable the
Flash data memory read documented in
Example 1. No other sequence of
commands will work, no exceptions.
5.2 Writing and Erasing Flash Data
Memory
Flash data memory is erased one row at a time and
written one byte at a time. The 64-byte array is made
up of eight rows. A row contains eight sequential bytes.
Row boundaries exist every eight bytes.
Generally, the procedure to write a byte of data to Flash
data memory is:
1. Identify the row containing the address where
the byte will be written.
2. If there is other information in that row that must
be saved, copy those bytes from Flash data
memory to RAM.
 2010 Microchip Technology Inc.
PIC16F526
3. Perform a row erase of the row of interest.
4. Write the new byte of data and any saved bytes
back to the appropriate addresses in Flash data
memory.
To prevent accidental corruption of the Flash data
memory, an unlock sequence is required to initiate a
write or erase cycle. This sequence requires that the bit
set instructions used to configure the EECON register
happen exactly as shown in Example 2 and Example 3,
depending on the operation requested.
5.2.1 ERASING FLASH DATA MEMORY
A row must be manually erased before writing new
data. The following sequence must be performed for a
single row erase.
1. Load EEADR with an address in the row to be
erased.
2. Set the FREE bit to enable the erase.
3. Set the WREN bit to enable write access to the
array.
4. Set the WR bit to initiate the erase cycle.
If the WREN bit is not set in the instruction cycle after
the FREE bit is set, the FREE bit will be cleared in
hardware.
If the WR bit is not set in the instruction cycle after the
WREN bit is set, the WREN bit will be cleared in
hardware.
Sample code that follows this procedure is included in
Example 2.
Program execution is suspended while the erase cycle
is in progress. Execution will continue with the
instruction following the one that sets the WR bit.
EXAMPLE 2: ERASING A FLASH DATA
MEMORY ROW
BANKSEL
MOVLW
MOVWF
BSF
BSF
BSF
EEADR
EE_ADR_ERASE
EEADR
EECON,FREE
EECON,WREN
EECON,WR
; LOAD ADDRESS OF ROW TO
; ERASE
;
; SELECT ERASE
; ENABLE WRITES
; INITITATE ERASE
Note 1: The FREE bit may be set by any com-
mand normally used by the core. How-
ever, the WREN and WR bits can only be
set using a series of BSF commands, as
documented in Example 1. No other
sequence of commands will work, no
exceptions.
2: Bits <5:3> of the EEADR register indicate
which row is to be erased.
DS41326D-page 23