PIC16F526 Datasheet, PDF (53/122 Pages) Microchip Technology – 14-Pin, 8-Bit Flash Microcontroller

8.5 Device Reset Timer (DRT)
On the PIC16F526 device, the DRT runs any time the
device is powered up. DRT runs from Reset and varies
based on oscillator selection and Reset type (see
Table 8-5).
The DRT operates on an internal RC oscillator. The
processor is kept in Reset as long as the DRT is active.
The DRT delay allows VDD to rise above VDD min. and
for the oscillator to stabilize.
Oscillator circuits based on crystals or ceramic resona-
tors require a certain time after power-up to establish a
stable oscillation. The on-chip DRT keeps the device in
a Reset condition after MCLR has reached a logic high
(VIH MCLR) level. Programming RB3/MCLR/VPP as
MCLR and using an external RC network connected to
the MCLR input is not required in most cases. This
allows savings in cost-sensitive and/or space restricted
applications, as well as allowing the use of the RB3/
MCLR/VPP pin as a general purpose input.
The Device Reset Time delays will vary from chip-to-
chip due to VDD, temperature and process variation.
See AC parameters for details.
The DRT will also be triggered upon a Watchdog Timer
time-out from Sleep. This is particularly important for
applications using the WDT to wake from Sleep mode
automatically.
Reset sources are POR, MCLR, WDT time-out and
wake-up on pin or comparator change. See
Section 8.9.2 “Wake-up from Sleep”, Notes 1, 2 and
3.
8.6 Watchdog Timer (WDT)
The Watchdog Timer (WDT) is a free running on-chip
RC oscillator, which does not require any external
components. This RC oscillator is separate from the
external RC oscillator of the RB5/OSC1/CLKIN pin and
the internal 4/8 MHz oscillator. This means that the
WDT will run even if the main processor clock has been
stopped, for example, by execution of a SLEEP
instruction. During normal operation or Sleep, a WDT
Reset or wake-up Reset, generates a device Reset.
The TO bit of the STATUS register will be cleared upon
a Watchdog Timer Reset.
The WDT can be permanently disabled by
programming the configuration WDTE as a ‘0’ (see
Section 8.1 “Configuration Bits”). Refer to the
PIC16F526 Programming Specifications to determine
how to access the Configuration Word.
PIC16F526
TABLE 8-5: TYPICAL DRT PERIODS
Oscillator
Configuration
POR Reset
Subsequent
Resets
HS, XT, LP
18 ms
18 ms
EC
1.125 ms
10 s
INTOSC, EXTRC
1.125 ms
10 s
8.6.1 WDT PERIOD
The WDT has a nominal time-out period of 18 ms, (with
no prescaler). If a longer time-out period is desired, a
prescaler with a division ratio of up to 1:128 can be
assigned to the WDT (under software control) by
writing to the OPTION register. Thus, a time-out period
of a nominal 2.3 seconds can be realized. These
periods vary with temperature, VDD and part-to-part
process variations (see DC specs).
Under worst-case conditions (VDD = Min., Temperature
= Max., max. WDT prescaler), it may take several
seconds before a WDT time-out occurs.
8.6.2
WDT PROGRAMMING
CONSIDERATIONS
The CLRWDT instruction clears the WDT and the
postscaler, if assigned to the WDT, and prevents it from
timing out and generating a device Reset.
The SLEEP instruction resets the WDT and the
postscaler, if assigned to the WDT. This gives the
maximum Sleep time before a WDT wake-up Reset.
 2010 Microchip Technology Inc.
DS41326D-page 53