PIC16F1934_11 Datasheet, PDF (368/472 Pages) Microchip Technology – 28/40/44-Pin Flash-Based, 8-Bit CMOS Microcontrollers

PIC16(L)F1934/6/7
TABLE 29-3: PIC16(L)F1938/9 ENHANCED INSTRUCTION SET (CONTINUED)
Mnemonic,
Operands
Description
14-Bit Opcode
Cycles
MSb
LSb
Status
Affected
Notes
CONTROL OPERATIONS
BRA
k
BRW
–
CALL
k
CALLW –
GOTO k
RETFIE k
RETLW k
RETURN –
Relative Branch
Relative Branch with W
Call Subroutine
Call Subroutine with W
Go to address
Return from interrupt
Return with literal in W
Return from Subroutine
2
11 001k kkkk kkkk
2
00 0000 0000 1011
2
10 0kkk kkkk kkkk
2
00 0000 0000 1010
2
10 1kkk kkkk kkkk
2
00 0000 0000 1001
2
11 0100 kkkk kkkk
2
00 0000 0000 1000
INHERENT OPERATIONS
CLRWDT –
NOP
–
OPTION –
RESET –
SLEEP –
TRIS
f
Clear Watchdog Timer
No Operation
Load OPTION_REG register with W
Software device Reset
Go into Standby mode
Load TRIS register with W
1
00 0000 0110 0100 TO, PD
1
00 0000 0000 0000
1
00 0000 0110 0010
1
00 0000 0000 0001
1
00 0000 0110 0011 TO, PD
1
00 0000 0110 0fff
C-COMPILER OPTIMIZED
ADDFSR n, k
Add Literal k to FSRn
1
11 0001 0nkk kkkk
MOVIW n mm
Move Indirect FSRn to W with pre/post inc/dec 1
00 0000 0001 0nmm Z
2, 3
modifier, mm
k[n]
Move INDFn to W, Indexed Indirect.
1
11 1111 0nkk kkkk Z
2
MOVWI n mm
Move W to Indirect FSRn with pre/post inc/dec 1
00 0000 0001 1nmm
2, 3
modifier, mm
k[n]
Move W to INDFn, Indexed Indirect.
1
11 1111 1nkk kkkk
2
Note 1:If the Program Counter (PC) is modified, or a conditional test is true, the instruction requires two cycles. The second cycle is
executed as a NOP.
2: If this instruction addresses an INDF register and the MSb of the corresponding FSR is set, this instruction will require
one additional instruction cycle.
3: See Table in the MOVIW and MOVWI instruction descriptions.
DS41364E-page 368
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