PIC16F1934_11 Datasheet, PDF (33/472 Pages) Microchip Technology – 28/40/44-Pin Flash-Based, 8-Bit CMOS Microcontrollers

TABLE 3-5: PIC16(L)F1936/1937 MEMORY MAP, BANKS 0-7
BANK 0
BANK 1
BANK 2
BANK 3
000h
001h
002h
003h
004h
005h
006h
007h
008h
009h
00Ah
00Bh
00Ch
00Dh
00Eh
00Fh
INDF0
INDF1
PCL
STATUS
FSR0L
FSR0H
FSR1L
FSR1H
BSR
WREG
PCLATH
INTCON
PORTA
PORTB
PORTC
PORTD⁽¹⁾
080h
081h
082h
083h
084h
085h
086h
087h
088h
089h
08Ah
08Bh
08Ch
08Dh
08Eh
08Fh
INDF0
INDF1
PCL
STATUS
FSR0L
FSR0H
FSR1L
FSR1H
BSR
WREG
PCLATH
INTCON
TRISA
TRISB
TRISC
TRISD⁽¹⁾
100h
101h
102h
103h
104h
105h
106h
107h
108h
109h
10Ah
10Bh
10Ch
10Dh
10Eh
10Fh
INDF0
INDF1
PCL
STATUS
FSR0L
FSR0H
FSR1L
FSR1H
BSR
WREG
PCLATH
INTCON
LATA
LATB
LATC
LATD⁽¹⁾
180h
181h
182h
183h
184h
185h
186h
187h
188h
189h
18Ah
18Bh
18Ch
18Dh
18Eh
18Fh
INDF0
INDF1
PCL
STATUS
FSR0L
FSR0H
FSR1L
FSR1H
BSR
WREG
PCLATH
INTCON
ANSELA
ANSELB
—
ANSELD⁽¹⁾
010h
011h
012h
013h
014h
015h
016h
017h
018h
019h
01Ah
01Bh
01Ch
01Dh
01Eh
01Fh
020h
PORTE
PIR1
PIR2
PIR3
—
TMR0
TMR1L
TMR1H
T1CON
T1GCON
TMR2
PR2
T2CON
—
CPSCON0
CPSCON1
090h
091h
092h
093h
094h
095h
096h
097h
098h
099h
09Ah
09Bh
09Ch
09Dh
09Eh
09Fh
0A0h
TRISE
PIE1
PIE2
PIE3
—
OPTION_REG
PCON
WDTCON
OSCTUNE
OSCCON
OSCSTAT
ADRESL
ADRESH
ADCON0
ADCON1
—
110h
111h
112h
113h
114h
115h
116h
117h
118h
119h
11Ah
11Bh
11Ch
11Dh
11Eh
11Fh
120h
LATE⁽¹⁾
CM1CON0
CM1CON1
CM2CON0
CM2CON1
CMOUT
BORCON
FVRCON
DACCON0
DACCON1
SRCON0
SRCON1
—
APFCON
—
—
190h
191h
192h
193h
194h
195h
196h
197h
198h
199h
19Ah
19Bh
19Ch
19Dh
19Eh
19Fh
1A0h
ANSELE⁽¹⁾
EEADRL
EEADRH
EEDATL
EEDATH
EECON1
EECON2
—
—
RCREG
TXREG
SPBRGL
SPBRGH
RCSTA
TXSTA
BAUDCON
06Fh
070h
General
Purpose
Register
96 Bytes
0EFh
0F0h
General
Purpose
Register
80 Bytes
Accesses
70h – 7Fh
16Fh
170h
General
Purpose
Register
80 Bytes
Accesses
70h – 7Fh
1EFh
1F0h
General
Purpose
Register
80 Bytes
Accesses
70h – 7Fh
07Fh
Legend:
Note 1:
0FFh
17Fh
= Unimplemented data memory locations, read as ‘0’.
Not available on PIC16(L)F1936.
1FFh
200h
201h
202h
203h
204h
205h
206h
207h
208h
209h
20Ah
20Bh
20Ch
20Dh
20Eh
20Fh
210h
211h
212h
213h
214h
215h
216h
217h
218h
219h
21Ah
21Bh
21Ch
21Dh
21Eh
21Fh
220h
26Fh
270h
27Fh
BANK 4
INDF0
INDF1
PCL
STATUS
FSR0L
FSR0H
FSR1L
FSR1H
BSR
WREG
PCLATH
INTCON
—
WPUB
—
—
WPUE
SSPBUF
SSPADD
SSPMSK
SSPSTAT
SSPCON1
SSPCON2
SSPCON3
—
—
—
—
—
—
—
—
General
Purpose
Register
80 Bytes
Accesses
70h – 7Fh
280h
281h
282h
283h
284h
285h
286h
287h
288h
289h
28Ah
28Bh
28Ch
28Dh
28Eh
28Fh
290h
291h
292h
293h
294h
295h
296h
297h
298h
299h
29Ah
29Bh
29Ch
29Dh
29Eh
29Fh
2A0h
2EFh
2F0h
2FFh
BANK 5
INDF0
INDF1
PCL
STATUS
FSR0L
FSR0H
FSR1L
FSR1H
BSR
WREG
PCLATH
INTCON
—
—
—
—
—
CCPR1L
CCPR1H
CCP1CON
PWM1CON
CCP1AS
PSTR1CON
—
CCPR2L
CCPR2H
CCP2CON
PWM2CON
CCP2AS
PSTR2CON
CCPTMRS0
CCPTMRS1
General
Purpose
Register
80 Bytes
Accesses
70h – 7Fh
BANK 6
300h
301h
302h
303h
304h
305h
306h
307h
308h
309h
30Ah
30Bh
30Ch
30Dh
30Eh
INDF0
INDF1
PCL
STATUS
FSR0L
FSR0H
FSR1L
FSR1H
BSR
WREG
PCLATH
INTCON
—
—
—
30Fh
—
310h
311h
312h
313h
314h
315h
316h
317h
318h
319h
31Ah
31Bh
31Ch
31Dh
31Eh
—
CCPR3L
CCPR3H
CCP3CON
PWM3CON
CCP3AS
PSTR3CON
—
CCPR4L
CCPR4H
CCP4CON
—
CCPR5L
CCPR5H
CCP5CON
31Fh
—
320h _{General Purpose}
Register
32Fh
16 Bytes
330h
36Fh
Unimplemented
Read as ‘0’
370h
Accesses
70h – 7Fh
37Fh
380h
381h
382h
383h
384h
385h
386h
387h
388h
389h
38Ah
38Bh
38Ch
38Dh
38Eh
38Fh
390h
391h
392h
393h
394h
395h
396h
397h
398h
399h
39Ah
39Bh
39Ch
39Dh
39Eh
39Fh
3A0h
3EFh
3F0h
3FFh
BANK 7
INDF0
INDF1
PCL
STATUS
FSR0L
FSR0H
FSR1L
FSR1H
BSR
WREG
PCLATH
INTCON
—
—
—
—
—
—
—
—
IOCBP
IOCBN
IOCBF
—
—
—
—
—
—
—
—
—
Unimplemented
Read as ‘0’
Accesses
70h – 7Fh