PIC18F23K20_10 Datasheet, PDF (267/456 Pages) Microchip Technology – 28/40/44-Pin Flash Microcontrollers with nanoWatt XLP Technology

PIC18F2XK20/4XK20
19.1.6 INTERRUPTS
The ADC module allows for the ability to generate an
interrupt upon completion of an Analog-to-Digital
Conversion. The ADC interrupt flag is the ADIF bit in
the PIR1 register. The ADC interrupt enable is the ADIE
bit in the PIE1 register. The ADIF bit must be cleared by
software.
Note:
The ADIF bit is set at the completion of
every conversion, regardless of whether
or not the ADC interrupt is enabled.
This interrupt can be generated while the device is
operating or while in Sleep. If the device is in Sleep, the
interrupt will wake-up the device. Upon waking from
Sleep, the next instruction following the SLEEP
instruction is always executed. If the user is attempting
to wake-up from Sleep and resume in-line code
execution, the global interrupt must be disabled. If the
global interrupt is enabled, execution will switch to the
Interrupt Service Routine. Please see Section 19.1.6
“Interrupts” for more information.
TABLE 19-1: ADC CLOCK PERIOD (TAD) VS. DEVICE OPERATING FREQUENCIES
ADC Clock Period (TAD)
Device Frequency (FOSC)
ADC Clock Source
ADCS<2:0>
64 MHz
16 MHz
4 MHz
1 MHz
FOSC/2
FOSC/4
FOSC/8
FOSC/16
FOSC/32
FOSC/64
FRC
000
31.25 ns⁽²⁾
125 ns⁽²⁾
500 ns⁽²⁾
2.0 s
100
62.5 ns⁽²⁾
250 ns⁽²⁾
1.0 s
4.0 s⁽³⁾
001
400 ns⁽²⁾
500 ns⁽²⁾
2.0 s
8.0 s⁽³⁾
101
250 ns⁽²⁾
1.0 s
4.0 s⁽³⁾
16.0 s⁽³⁾
010
500 ns⁽²⁾
2.0 s
8.0 s⁽³⁾
32.0 s⁽³⁾
110
1.0 s
4.0 s⁽³⁾
16.0 s⁽³⁾
64.0 s⁽³⁾
x11
1-4 s^(1,4)
1-4 s^(1,4)
1-4 s^(1,4)
1-4 s^(1,4)
Legend: Shaded cells are outside of recommended range.
Note 1: The FRC source has a typical TAD time of 1.7 s.
2: These values violate the minimum required TAD time.
3: For faster conversion times, the selection of another clock source is recommended.
4: When the device frequency is greater than 1 MHz, the FRC clock source is only recommended if the
conversion will be performed during Sleep.
19.1.7 RESULT FORMATTING
The 10-bit A/D conversion result can be supplied in two
formats, left justified or right justified. The ADFM bit of
the ADCON2 register controls the output format.
Figure 19-2 shows the two output formats.
FIGURE 19-2:
10-BIT A/D CONVERSION RESULT FORMAT
ADRESH
(ADFM = 0) MSB
bit 7
bit 0
10-bit A/D Result
(ADFM = 1)
bit 7
MSB
bit 0
Unimplemented: Read as ‘0’
ADRESL
LSB
bit 7
bit 0
Unimplemented: Read as ‘0’
LSB
bit 7
bit 0
10-bit A/D Result
 2010 Microchip Technology Inc.
DS41303G-page 267