PIC18F23K20_10 Datasheet, PDF (262/456 Pages) Microchip Technology – 28/40/44-Pin Flash Microcontrollers with nanoWatt XLP Technology

PIC18F2XK20/4XK20
18.4.2 SYNCHRONOUS SLAVE MODE
The following bits are used to configure the EUSART
for Synchronous slave operation:
• SYNC = 1
• CSRC = 0
• SREN = 0 (for transmit); SREN = 1 (for receive)
• CREN = 0 (for transmit); CREN = 1 (for receive)
• SPEN = 1
Setting the SYNC bit of the TXSTA register configures
the device for synchronous operation. Clearing the
CSRC bit of the TXSTA register configures the device as
a slave. Clearing the SREN and CREN bits of the RCSTA
register ensures that the device is in the Transmit mode,
otherwise the device will be configured to receive. Setting
the SPEN bit of the RCSTA register enables the
EUSART. If the RX/DT or TX/CK pins are shared with an
analog peripheral the analog I/O functions must be
disabled by clearing the corresponding ANSEL bits.
RX/DT and TX/CK pin output drivers must be disabled
by setting the corresponding TRIS bits.
18.4.2.1 EUSART Synchronous Slave
Transmit
The operation of the Synchronous Master and Slave
modes are identical (see Section 18.4.1.3
“Synchronous Master Transmission”), except in the
case of the Sleep mode.
If two words are written to the TXREG and then the
SLEEP instruction is executed, the following will occur:
1. The first character will immediately transfer to
the TSR register and transmit.
2. The second word will remain in TXREG register.
3. The TXIF bit will not be set.
4. After the first character has been shifted out of
TSR, the TXREG register will transfer the second
character to the TSR and the TXIF bit will now be
set.
5. If the PEIE and TXIE bits are set, the interrupt
will wake the device from Sleep and execute the
next instruction. If the GIE bit is also set, the
program will call the Interrupt Service Routine.
18.4.2.2 Synchronous Slave Transmission
Set-up:
1. Set the SYNC and SPEN bits and clear the
CSRC bit.
2. Set the RX/DT and TX/CK TRIS controls to ‘1’.
3. Clear the CREN and SREN bits.
4. If using interrupts, ensure that the GIE and PEIE
bits of the INTCON register are set and set the
TXIE bit.
5. If 9-bit transmission is desired, set the TX9 bit.
6. Enable transmission by setting the TXEN bit.
7. If 9-bit transmission is selected, insert the Most
Significant bit into the TX9D bit.
8. Start transmission by writing the Least
Significant 8 bits to the TXREG register.
TABLE 18-9: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE TRANSMISSION
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset
Values
on page
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF
59
PIR1
PSPIF⁽¹⁾ ADIF
RCIF
TXIF
SSPIF CCP1IF TMR2IF TMR1IF
62
PIE1
PSPIE⁽¹⁾ ADIE
RCIE
TXIE
SSPIE CCP1IE TMR2IE TMR1IE
62
IPR1
PSPIP⁽¹⁾ ADIP
RCIP
TXIP
SSPIP CCP1IP TMR2IP TMR1IP
62
RCSTA
SPEN
RX9
SREN CREN ADDEN FERR OERR RX9D
61
TRISC
TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0
62
TXREG
EUSART Transmit Register
61
TXSTA
CSRC
TX9
TXEN SYNC SENDB BRGH TRMT TX9D
61
BAUDCON ABDOVF RCIDL DTRXP CKTXP BRG16
—
WUE ABDEN
61
SPBRGH EUSART Baud Rate Generator Register, High Byte
61
SPBRG
EUSART Baud Rate Generator Register, Low Byte
61
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for synchronous master transmission.
Note 1: Reserved in PIC18F2XK20 devices; always maintain these bits clear.
DS41303G-page 262
 2010 Microchip Technology Inc.