PIC18F23K20_10 Datasheet, PDF (249/456 Pages) Microchip Technology – 28/40/44-Pin Flash Microcontrollers with nanoWatt XLP Technology

PIC18F2XK20/4XK20
18.3 EUSART Baud Rate Generator
(BRG)
The Baud Rate Generator (BRG) is an 8-bit or 16-bit
timer that is dedicated to the support of both the
asynchronous and synchronous EUSART operation.
By default, the BRG operates in 8-bit mode. Setting the
BRG16 bit of the BAUDCON register selects 16-bit
mode.
The SPBRGH:SPBRG register pair determines the
period of the free running baud rate timer. In
Asynchronous mode the multiplier of the baud rate
period is determined by both the BRGH bit of the TXSTA
register and the BRG16 bit of the BAUDCON register. In
Synchronous mode, the BRGH bit is ignored.
Table 18-3 contains the formulas for determining the
baud rate. Example 18-1 provides a sample calculation
for determining the baud rate and baud rate error.
Typical baud rates and error values for various
asynchronous modes have been computed for your
convenience and are shown in Table 18-5. It may be
advantageous to use the high baud rate (BRGH = 1),
or the 16-bit BRG (BRG16 = 1) to reduce the baud rate
error. The 16-bit BRG mode is used to achieve slow
baud rates for fast oscillator frequencies.
Writing a new value to the SPBRGH, SPBRG register
pair causes the BRG timer to be reset (or cleared). This
ensures that the BRG does not wait for a timer overflow
before outputting the new baud rate.
If the system clock is changed during an active receive
operation, a receive error or data loss may result. To
avoid this problem, check the status of the RCIDL bit to
make sure that the receive operation is Idle before
changing the system clock.
EXAMPLE 18-1: CALCULATING BAUD
RATE ERROR
For a device with FOSC of 16 MHz, desired baud rate
of 9600, Asynchronous mode, 8-bit BRG:
Desired Baud Rate = _{6---4----}--[---S---P---B----R----G--F--H--^O--:--^S_S---^C_{P----B----R---G-----]----+-----1----}
Solving for SPBRGH:SPBRG:
----------------F----^O----^S---^C------------------
X = -D----e---s--i--r--e---d----B----a---u---d----R----a---t--e- – 1
64
= -1-----6------09--------06-----00-----00------0-------0--- – 1
64
= 25.042 = 25
Calculated Baud Rate = _{6--1-4--6--}-0-2--0-5--0---+0---0--1-0---_
= 9615
Error = ^{C-----a--l--c---.---B---a---u--D--d---e-R-s---ia-r--t-ee--d---–}--B--D-a---eu---sd--i--r-R-e---ad---t-e-B---a---u---d-----R---a---t--e---
= ^---9---6---1---95---6-^–--0---09---6---0---0---^- = 0.16%
TABLE 18-3: BAUD RATE FORMULAS
Configuration Bits
SYNC
BRG16
BRGH
BRG/EUSART Mode
0
0
0
0
1
1
Legend:
0
0
8-bit/Asynchronous
0
1
8-bit/Asynchronous
1
0
16-bit/Asynchronous
1
1
16-bit/Asynchronous
0
x
8-bit/Synchronous
1
x
16-bit/Synchronous
x = Don’t care, n = value of SPBRGH, SPBRG register pair
Baud Rate Formula
FOSC/[64 (n+1)]
FOSC/[16 (n+1)]
FOSC/[4 (n+1)]
TABLE 18-4: REGISTERS ASSOCIATED WITH BAUD RATE GENERATOR
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2 Bit 1
TXSTA
CSRC
TX9
TXEN SYNC SENDB BRGH TRMT
RCSTA
SPEN
RX9
SREN CREN ADDEN FERR OERR
BAUDCON ABDOVF RCIDL DTRXP CKTXP BRG16
—
WUE
SPBRGH EUSART Baud Rate Generator Register, High Byte
SPBRG EUSART Baud Rate Generator Register, Low Byte
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the BRG.
Bit 0
TX9D
RX9D
ABDEN
Reset Values
on page
61
61
61
61
61
 2010 Microchip Technology Inc.
DS41303G-page 249