PIC18F23K20_10 Datasheet, PDF (152/456 Pages) Microchip Technology – 28/40/44-Pin Flash Microcontrollers with nanoWatt XLP Technology

PIC18F2XK20/4XK20
11.4.4
OPERATION IN POWER-MANAGED
MODES
In Sleep mode, the TMR2 register will not increment
and the state of the module will not change. If the CCPx
pin is driving a value, it will continue to drive that value.
When the device wakes up, TMR2 will continue from its
previous state.
In PRI_IDLE mode, the primary clock will continue to
clock the CCP module without change. In all other
power-managed modes, the selected power-managed
mode clock will clock Timer2. Other power-managed
mode clocks will most likely be different than the
primary clock frequency.
11.4.5
CHANGES IN SYSTEM CLOCK
FREQUENCY
The PWM frequency is derived from the system clock
frequency. Any changes in the system clock frequency
will result in changes to the PWM frequency. See
Section 2.0 “Oscillator Module (With Fail-Safe
Clock Monitor)” for additional details.
11.4.6 EFFECTS OF RESET
Any Reset will force all ports to Input mode and the
CCP registers to their Reset states.
11.4.7 SETUP FOR PWM OPERATION
The following steps should be taken when configuring
the CCP module for PWM operation:
1. Disable the PWM pin (CCPx) output drivers by
setting the associated TRIS bit.
2. For the ECCP module only: Select the desired
PWM outputs (P1A through P1D) by setting the
appropriate steering bits of the PSTRCON
register.
3. Set the PWM period by loading the PR2 register.
4. Configure the CCP module for the PWM mode
by loading the CCPxCON register with the
appropriate values.
5. Set the PWM duty cycle by loading the CCPRxL
register and CCPx bits of the CCPxCON register.
6. Configure and start Timer2:
• Clear the TMR2IF interrupt flag bit of the
PIR1 register.
• Set the Timer2 prescale value by loading the
T2CKPS bits of the T2CON register.
• Enable Timer2 by setting the TMR2ON bit of
the T2CON register.
7. Enable PWM output after a new PWM cycle has
started:
• Wait until Timer2 overflows (TMR2IF bit of
the PIR1 register is set).
• Enable the CCPx pin output driver by
clearing the associated TRIS bit.
DS41303G-page 152
 2010 Microchip Technology Inc.