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PIC18F23K20_10 Datasheet, PDF (171/456 Pages) Microchip Technology – 28/40/44-Pin Flash Microcontrollers with nanoWatt XLP Technology
PIC18F2XK20/4XK20
FIGURE 15-2:
TIMER3 BLOCK DIAGRAM (16-BIT READ/WRITE MODE)
Timer1 Oscillator
Timer1 Clock Input
1
T13CKI/T1OSO
T1OSI
T1OSCEN(1)
T3CKPS<1:0>
T3SYNC
TMR3ON
1
FOSC/4
Internal
Clock
0
TMR3CS
Prescaler
1, 2, 4, 8
2
Synchronize
Detect
0
Sleep Input
Timer3
On/Off
CCP1/CCP2 Special Event Trigger
CCP1/CCP2 Select from T3CON<6,3>
Clear TMR3
TMR3L
TMR3
High Byte
8
Set
TMR3IF
on Overflow
Read TMR1L
8
8
Write TMR1L
TMR3H
8
8
Internal Data Bus
Note 1: When enable bit, T1OSCEN, is cleared, the inverter and feedback resistor are turned off to eliminate power drain.
15.2 Timer3 16-Bit Read/Write Mode
Timer3 can be configured for 16-bit reads and writes
(see Figure 15-2). When the RD16 control bit of the
T3CON register is set, the address for TMR3H is
mapped to a buffer register for the high byte of Timer3.
A read from TMR3L will load the contents of the high
byte of Timer3 into the Timer3 High Byte Buffer regis-
ter. This provides the user with the ability to accurately
read all 16 bits of Timer1 without having to determine
whether a read of the high byte, followed by a read of
the low byte, has become invalid due to a rollover
between reads.
A write to the high byte of Timer3 must also take place
through the TMR3H Buffer register. The Timer3 high
byte is updated with the contents of TMR3H when a
write occurs to TMR3L. This allows a user to write all
16 bits to both the high and low bytes of Timer3 at once.
The high byte of Timer3 is not directly readable or
writable in this mode. All reads and writes must take
place through the Timer3 High Byte Buffer register.
Writes to TMR3H do not clear the Timer3 prescaler.
The prescaler is only cleared on writes to TMR3L.
15.3 Using the Timer1 Oscillator as the
Timer3 Clock Source
The Timer1 internal oscillator may be used as the clock
source for Timer3. The Timer1 oscillator is enabled by
setting the T1OSCEN bit of the T1CON register. To use
it as the Timer3 clock source, the TMR3CS bit must
also be set. As previously noted, this also configures
Timer3 to increment on every rising edge of the
oscillator source.
The Timer1 oscillator is described in Section 13.0
“Timer1 Module”.
15.4 Timer3 Interrupt
The TMR3 register pair (TMR3H:TMR3L) increments
from 0000h to FFFFh and overflows to 0000h. The
Timer3 interrupt, if enabled, is generated on overflow
and is latched in interrupt flag bit, TMR3IF of the PIR2
register. This interrupt can be enabled or disabled by
setting or clearing the Timer3 Interrupt Enable bit,
TMR3IE of the PIE2 register.
 2010 Microchip Technology Inc.
DS41303G-page 171