PIC16F636T-I Datasheet, PDF (26/234 Pages) Microchip Technology – 8/14-Pin, Flash-Based 8-Bit CMOS Microcontrollers with nanoWatt Technology

PIC12F635/PIC16F636/639
TABLE 2-4: PIC16F636/639 SPECIAL FUNCTION REGISTERS SUMMARY BANK 1
Addr Name
Bit 7
Bit 6
Bit 5
Bit 4 Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR/BOR/
WUR
Page
Bank 1
80h INDF
Addressing this location uses contents of FSR to address data memory
(not a physical register)
xxxx xxxx 32,137
81h OPTION_REG RAPU INTEDG T0CS T0SE PSA
PS2
PS1
PS0 1111 1111 ^63,137
82h PCL
Program Counter’s (PC) Least Significant Byte
0000 0000 32,137
83h STATUS
IRP
RP1
RP0
TO
PD
Z
DC
C 0001 1xxx 26,137
84h FSR
Indirect Data Memory Address Pointer
xxxx xxxx 32,137
85h TRISA
—
— TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 --11 1111 --11 1111
86h
—
Unimplemented
—
—
87h TRISC
—
— TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 --11 1111 --11 1111
88h
—
Unimplemented
—
—
89h
—
Unimplemented
—
—
8Ah PCLATH
8Bh INTCON
8Ch PIE1
8Dh
—
—
—
GIE
PEIE
EEIE LVDIE
Unimplemented
—
T0IE
CRIE
Write Buffer for upper 5 bits of Program Counter ---0 0000
INTE RAIE T0IF
INTF RAIF⁽³⁾ 0000 000x
C2IE C1IE OSFIE
— TMR1IE 0000 00-0
—
32,137
28,137
29,137
—
8Eh PCON
—
— ULPWUE SBOREN WUR
—
POR BOR --01 q-qq --0u u-uu
8Fh OSCCON
—
IRCF2 IRCF1 IRCF0 OSTS HTS
LTS
SCS -110 q000 -110 x000
90h OSCTUNE
—
—
—
TUN4 TUN3 TUN2 TUN1 TUN0 ---0 0000 ---u uuuu
91h
—
Unimplemented
—
—
92h
—
Unimplemented
—
—
93h
—
Unimplemented
—
—
94h LVDCON
—
—
IRVST LVDEN —
LVDL2 LVDL1 LVDL0 --00 -000 --00 -000
95h WPUDA⁽²⁾
—
— WPUDA5 WPUDA4 — WPUDA2 WPUDA1 WPUDA0 --11 -111 --11 -111
96h IOCA
97h WDA⁽²⁾
—
—
IOCA5 IOCA4 IOCA3 IOCA2 IOCA1 IOCA0 --00 0000 --00 0000
—
—
WDA5 WDA4
—
WDA2 WDA1 WDA0 --11 -111 --11 -111
9Bh
—
Unimplemented
—
—
99h VRCON
VREN
—
VRR
—
VR3
VR2
VR1
VR0 0-0- 0000 0-0- 0000
9Ah EEDAT
EEDAT7 EEDAT6 EEDAT5 EEDAT4 EEDAT3 EEDAT2 EEDAT1 EEDAT0 0000 0000 0000 0000
9Bh EEADR
EEADR7 EEADR6 EEADR5 EEADR4 EEADR3 EEADR2 EEADR1 EEADR0 0000 0000 0000 0000
9Ch EECON1
—
—
—
— WRERR WREN WR
RD ---- x000 ---- q000
9Dh EECON2
EEPROM Control Register 2 (not a physical register)
---- ---- ---- ----
9Eh
—
Unimplemented
—
—
9Fh
—
Unimplemented
—
—
Legend:
Note 1:
2:
3:
– = Unimplemented locations read as ‘0’, u = unchanged, x = unknown, q = value depends on condition,
shaded = unimplemented
Other (non Power-up) Resets include MCLR Reset and Watchdog Timer Reset during normal operation.
RA3 pull-up is enabled when pin is configured as MCLR in the Configuration Word register.
MCLR and WDT Reset do not affect the previous value data latch. The RAIF bit will be cleared upon Reset but will set
again if the mismatch exists.
DS41232D-page 24
© 2007 Microchip Technology Inc.