PIC16F636T-I Datasheet, PDF (137/234 Pages) Microchip Technology – 8/14-Pin, Flash-Based 8-Bit CMOS Microcontrollers with nanoWatt Technology

PIC12F635/PIC16F636/639
12.7 Time-out Sequence
On power-up, the time-out sequence is as follows: first,
PWRT time-out is invoked after POR has expired, then
OST is activated after the PWRT time-out has expired.
The total time-out will vary based on oscillator
Configuration and PWRTE bit status. For example, in
EC mode with PWRTE bit erased (PWRT disabled),
there will be no time-out at all. Figure 12-4, Figure 12-5
and Figure 12-6 depict time-out sequences. The device
can execute code from the INTOSC, while OST is active,
by enabling Two-Speed Start-up or Fail-Safe Clock
Monitor (See Section 3.7.2 “Two-Speed Start-up
Sequence” and Section 3.8 “Fail-Safe Clock
Monitor”).
Since the time-outs occur from the POR pulse, if MCLR
is kept low long enough, the time-outs will expire. Then
bringing MCLR high will begin execution immediately
(see Figure 12-5). This is useful for testing purposes or
to
synchronize
more
than
one
PIC12F635/PIC16F636/639 device operating in parallel.
Table 12-5 shows the Reset conditions for some
special registers, while Table 12-4 shows the Reset
conditions for all the registers.
12.8 Power Control (PCON) Register
The Power Control register, PCON (address 8Eh), has
two Status bits to indicate what type of Reset that last
occurred.
Bit 0 is BOR (Brown-out). BOR is unknown on
Power-on Reset. It must then be set by the user and
checked on subsequent Resets to see if BOR = 0,
indicating that a Brown-out has occurred. The BOR
Status bit is a “don’t care” and is not necessarily
predictable if the brown-out circuit is disabled
(BOREN<1:0> = 00 in the Configuration Word
register).
Bit 1 is POR (Power-on Reset). It is a ‘0’ on Power-on
Reset and unaffected otherwise. The user must write a
‘1’ to this bit following a Power-on Reset. On a
subsequent Reset, if POR is ‘0’, it will indicate that a
Power-on Reset has occurred (i.e., VDD may have
gone too low).
For more information, see Section 4.2.3 “Ultra
Low-Power Wake-up” and Section 12.6 “Brown-out
Reset (BOR)”.
TABLE 12-1: TIME-OUT IN VARIOUS SITUATIONS
Oscillator
Configuration
Power-up
PWRTE = 0
PWRTE = 1
Brown-out Reset
PWRTE = 0
PWRTE = 1
XT, HS, LP
TPWRT + 1024 • TOSC 1024 • TOSC
RC, EC, INTOSC
TPWRT
—
TPWRT + 1024 • TOSC
TPWRT
1024 • TOSC
—
Wake-up
from Sleep
1024 • TOSC
—
TABLE 12-2: SUMMARY OF REGISTERS ASSOCIATED WITH BROWN-OUT RESET
Name
Bit 9
Bit 8
Bit 7 Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Value on
all other
Resets⁽¹⁾
CONFIG⁽²⁾ BOREN1 BOREN0 CPD
CP MCLRE PWRTE WDTE FOSC2 FOSC1 FOSC0
—
—
PCON
—
— ULPWUE SBOREN WUR
—
POR BOR --01 --qq --0u --uu
STATUS
Legend:
Note 1:
2:
IRP
RP1
RP0
TO
PD
Z
DC
C
0001 1xxx 000q quuu
u = unchanged, x = unknown, – = unimplemented bit, reads as ‘0’, q = value depends on condition. Shaded cells are not used by BOR.
Other (non Power-up) Resets include MCLR Reset and Watchdog Timer Reset during normal operation.
See Configuration Word register (Register 12-1) for operation of all register bits.
TABLE 12-3: PCON BITS AND THEIR SIGNIFICANCE
POR
BOR
WUR
TO
PD
Condition
0
x
x
1
1 Power-on Reset
u
0
u
1
1 Brown-out Reset
u
u
u
0
u WDT Reset
u
u
u
0
0 WDT Wake-up
u
u
u
u
u MCLR Reset during normal operation
u
u
u
1
u
u
0
1
u
0
u
1
Legend: u = unchanged, x = unknown
0 MCLR Reset during Sleep
0 Wake-up Reset during Sleep
1 Brown-out Reset during Sleep
© 2007 Microchip Technology Inc.
DS41232D-page 135