PIC16F636T-I Datasheet, PDF (100/234 Pages) Microchip Technology – 8/14-Pin, Flash-Based 8-Bit CMOS Microcontrollers with nanoWatt Technology

PIC12F635/PIC16F636/639
11.6 AGC Control
The AGC controls the variable attenuator to limit the
internal signal voltage to avoid saturation of internal
amplifiers and demodulators (Refer to Section 11.4
“Variable Attenuator”).
The signal levels from all 3 channels are combined
such that AGC attenuates all 3 channels uniformly in
respect to the channel with the strongest signal.
Note:
The AGC control function is accomplished
by the device itself. The user cannot
control its function.
11.7 Fixed Gain Amplifiers 1 and 2
FGA1 and FGA2 provides a maximum two-stage gain
of 40 dB.
Note: The user cannot control the gain of these
two amplifiers.
11.8 Auto Channel Selection
The Auto Channel Selection feature is enabled if the
Auto Channel Select bit AUTOCHSEL<8> in Configu-
ration Register 5 (Register 11-6) is set, and disabled if
the bit is cleared. When this feature is active (i.e.,
AUTOCHSE <8> = 1), the control circuit checks the
demodulator output of each input channel immediately
after the AGC settling time (TSTAB). If the output is high,
it allows this channel to pass data, otherwise it is
blocked.
The status of this operation is monitored by AFE Status
Register 7 bits <8:6> (Register 11-8). These bits indicate
the current status of the channel selection activity, and
automatically updates for every Soft Reset period. The
auto channel selection function resets after each Soft
Reset (or after Inactivity timer time-out). Therefore, the
blocked channels are reenabled after Soft Reset.
This feature can make the output signal cleaner by
blocking any channel that was not high at the end of
TAGC. This function works only for demodulated data
output, and is not applied for carrier clock or RSSI
output.
11.9 Carrier Clock Detector
The Detector senses the input carrier cycles. The
output of the Detector switches digitally at the signal
carrier frequency. Carrier clock output is available
when the output is selected by the DATOUT bit in the
AFE Configuration Register 1 (Register 11-2).
11.10 Demodulator
The Demodulator consists of a full-wave rectifier, low
pass filter, peak detector and Data Slicer that detects
the envelope of the input signal.
11.11 Data Slicer
The Data Slicer consists of a reference generator and
comparator. The Data Slicer compares the input with
the reference voltage. The reference voltage comes
from the minimum modulation depth requirement
setting and input peak voltage. The data from all 3
channels are OR’d together and sent to the output
enable filter.
11.12 Output Enable Filter
The Output Enable Filter enables the LFDATA output
once the incoming signal meets the wake-up sequence
requirements (see Section 11.15 “Configurable
Output Enable Filter”).
11.13 RSSI (Received Signal Strength
Indicator)
The RSSI provides a current which is proportional to the
input signal amplitude (see Section 11.31.3 “Received
Signal Strength Indicator (RSSI) Output”).
11.14 Analog Front-End Timers
The AFE has an internal 32 kHz RC oscillator. The
oscillator is used in several timers:
• Inactivity timer
• Alarm timer
• Pulse Width timer
• Period timer
• AGC settling timer
11.14.1 RC OSCILLATOR
The RC oscillator is low power, 32 kHz ± 10% over
temperature and voltage variations.
DS41232D-page 98
© 2007 Microchip Technology Inc.