PIC24FJ128GA010_12 Datasheet, PDF (176/258 Pages) Microchip Technology – 64/80/100-Pin, General Purpose, 16-Bit Flash Microcontrollers

PIC24FJ128GA010 FAMILY
FIGURE 20-2:
CRC GENERATOR RECONFIGURED FOR x¹⁶ + x¹² + x⁵ + 1
XOR
SDOx
DQ
BIT 0
DQ
BIT 4
DQ
BIT 5
DQ
BIT 12
p_clk
p_clk
p_clk
p_clk
DQ
BIT 15
p_clk
CRC Read Bus
CRC Write Bus
20.3 User Interface
20.3.1 DATA INTERFACE
To start serial shifting, a ‘1’ must be written to the
CRCGO bit.
The module incorporates a FIFO that is 8-deep when
PLEN<3:0> (CRCCON<3:0>) > 7 and 16-deep other-
wise. The data for which the CRC is to be calculated
must first be written into the FIFO. The smallest data
element that can be written into the FIFO is one byte.
For example, if PLEN = 5, then the size of the data is
PLEN + 1 = 6. The data must be written as follows:
data[5:0] = crc_input[5:0]
data[7:6] = ‘bxx
Once data is written into the CRCWDAT MSb (as
defined by PLEN), the value of the VWORD<4:0> bits
(CRCCON<12:8>) increment by one. The serial shifter
starts shifting data into the CRC engine when
CRCGO = 1 and VWORD > 0. When the MSb is
shifted out, VWORD decrements by one. The serial
shifter continues shifting until the VWORD reaches 0.
Therefore, for a given value of PLEN, it will take
(PLEN<3:0> + 1)/2 x VWORD number of clock cycles
to complete the CRC calculations.
When VWORD reaches 8 (or 16), the CRCFUL bit will
be set. When VWORD reaches 0, the CRCMPT bit will
be set.
To continually feed data into the CRC engine, the rec-
ommended mode of operation is to initially “prime” the
FIFO with a sufficient number of words, so no interrupt
is generated before the next word can be written. Once
that is done, start the CRC by setting the CRCGO bit to
‘1’. From that point onward, the VWORD bits should be
polled. If they read less than 8 or 16, another word can
be written into the FIFO.
To empty words already written into a FIFO, the
CRCGO bit must be set to ‘1’ and the CRC shifter
allowed to run until the CRCMPT bit is set.
Also, to get the correct CRC reading, it will be
necessary to wait for the CRCMPT bit to go high before
reading the CRCWDAT register.
If a word is written when the CRCFUL bit is set, the
VWORD Pointer will roll over to 0. The hardware will
then behave as if the FIFO is empty. However, the con-
dition to generate an interrupt will not be met; therefore,
no interrupt will be generated (see Section 20.3.2
“Interrupt Operation”).
At least one instruction cycle must pass after a write to
CRCWDAT before a read of the VWORD bits is done.
20.3.2 INTERRUPT OPERATION
When VWORD<4:0> make a transition from a value of
‘1’ to ‘0’, an interrupt will be generated.
DS39747F-page 176
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