PIC24FJ128GA010_12 Datasheet, PDF (137/258 Pages) Microchip Technology – 64/80/100-Pin, General Purpose, 16-Bit Flash Microcontrollers

PIC24FJ128GA010 FAMILY
16.0 INTER-INTEGRATED CIRCUIT
(I²C™)
Note:
This data sheet summarizes the features of
this group of PIC24F devices. It is not
intended to be a comprehensive reference
source. Refer to Section 24. “Inter-
Integrated Circuit™ (I²C™)” (DS39702)
in the “PIC24F Family Reference Manual”
for more information.
The Inter-Integrated Circuit (I²C) module is a serial
interface useful for communicating with other periph-
eral or microcontroller devices. These peripheral
devices may be serial EEPROMs, display drivers, A/D
Converters, etc.
The I²C module supports these features:
• Independent master and slave logic
• 7-bit and 10-bit device addresses
• General call address, as defined in the I²C protocol
• Clock stretching to provide delays for the
processor to respond to a slave data request
• Both 100 kHz and 400 kHz bus specifications.
• Configurable address masking
• Multi-Master modes to prevent loss of messages
in arbitration
• Bus Repeater mode, allowing the acceptance of
all messages as a slave, regardless of the
address
• Automatic SCL
A block diagram of the module is shown in Figure 16-1.
16.1 Communicating as a Master in a
Single Master Environment
The details of sending a message in Master mode
depends on the communications protocol for the device
being communicated with. Typically, the sequence of
events is as follows:
1. Assert a Start condition on SDAx and SCLx.
2. Send the I²C device address byte to the slave
with a write indication.
3. Wait for and verify an Acknowledge from the
slave.
4. Send the first data byte (sometimes known as
the command) to the slave.
5. Wait for and verify an Acknowledge from the
slave.
6. Send the serial memory address low byte to the
slave.
7. Repeat Steps 4 and 5 until all data bytes are
sent.
8. Assert a Repeated Start condition on SDAx and
SCLx.
9. Send the device address byte to the slave with
a read indication.
10. Wait for and verify an Acknowledge from the
slave.
11. Enable master reception to receive serial
memory data.
12. Generate an ACK or NACK condition at the end
of a received byte of data.
13. Generate a Stop condition on SDAx and SCLx.
 2005-2012 Microchip Technology Inc.
DS39747F-page 137