PIC24FJ128GA010_12 Datasheet, PDF (150/258 Pages) Microchip Technology – 64/80/100-Pin, General Purpose, 16-Bit Flash Microcontrollers

PIC24FJ128GA010 FAMILY
REGISTER 17-2: UxSTA: UARTx STATUS AND CONTROL REGISTER
R/W-0
UTXISEL1
bit 15
R/W-0
TXINV
R/W-0
UTXISEL0
U-0
R/W-0, HC
R/W-0
—
UTXBRK
UTXEN
R-0
UTXBF
R-1
TRMT
bit 8
R/W-0
URXISEL1
bit 7
R/W-0
URXISEL0
R/W-0
ADDEN
R-1
RIDLE
R-0
PERR
R-0
FERR
R/C-0
OERR
R-0
URXDA
bit 0
Legend:
R = Readable bit
-n = Value at POR
C = Clearable bit
W = Writable bit
‘1’ = Bit is set
HC = Hardware Clearable bit
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 15,13
bit 14
bit 12
bit 11
bit 10
bit 9
bit 8
bit 7-6
bit 5
UTXISEL<1:0>: Transmission Interrupt Mode Selection bits
11 = Reserved; do not use
10 = Interrupt when a character is transferred to the Transmit Shift Register and as a result, the transmit
buffer becomes empty
01 = Interrupt when the last character is shifted out of the Transmit Shift Register; all transmit operations
are completed
00 = Interrupt when a character is transferred to the Transmit Shift Register (this implies there is at least
one character open in the transmit buffer)
TXINV: Transmit Polarity Inversion bit
IREN = 0:
1 = TX Idle state is ‘0’
0 = TX Idle state is ‘1’
IREN = 1:
1 = IrDA^® encoded TX Idle state is ‘1’
0 = IrDA encoded TX Idle state is ‘0’
Unimplemented: Read as ‘0’
UTXBRK: Transmit Break bit
1 = Sends Sync Break on next transmission – Start bit, followed by twelve ‘0’ bits, followed by Stop bit;
cleared by hardware upon completion
0 = Sync Break transmission is disabled or completed
UTXEN: Transmit Enable bit
1 = Transmit is enabled, UxTX pin controlled by UARTx
0 = Transmit is disabled, any pending transmission is aborted and the buffer is reset. UxTX pin is controlled
by the PORT.
UTXBF: Transmit Buffer Full Status bit (read-only)
1 = Transmit buffer is full
0 = Transmit buffer is not full, at least one more character can be written
TRMT: Transmit Shift Register Empty bit (read-only)
1 = Transmit Shift Register is empty and transmit buffer is empty (the last transmission has completed)
0 = Transmit Shift Register is not empty, a transmission is in progress or queued
URXISEL<1:0>: Receive Interrupt Mode Selection bits
11 = Interrupt is set on RSR transfer, making the receive buffer full (i.e., has 4 data characters)
10 = Interrupt is set on RSR transfer, making the receive buffer 3/4 full (i.e., has 3 data characters)
0x = Interrupt is set when any character is received and transferred from the RSR to the receive buffer;
receive buffer has one or more characters
ADDEN: Address Character Detect bit (bit 8 of received data = 1)
1 = Address Detect mode is enabled. If 9-bit mode is not selected, this does not take effect.
0 = Address Detect mode is disabled
DS39747F-page 150
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