PIC24FJ128GA010_12 Datasheet, PDF (164/258 Pages) Microchip Technology – 64/80/100-Pin, General Purpose, 16-Bit Flash Microcontrollers

PIC24FJ128GA010 FAMILY
19.1 RTCC Module Registers
The RTCC module registers are organized into three
categories:
• RTCC Control Registers
• RTCC Value Registers
• Alarm Value Registers
19.1.1 REGISTER MAPPING
To limit the register interface, the RTCC Timer and
Alarm Time registers are accessed through corre-
sponding register pointers. The RTCC Value register
window (RTCVALH and RTCVALL) uses the RTCPTR
bits (RCFGCAL<9:8>) to select the desired Timer
register pair (see Table 19-1). By writing the RTCVALH
byte, the RTCC Pointer value, RTCPTR<1:0>, decre-
ments by one until it reaches ‘00’. Once it reaches ‘00’,
the MINUTES and SECONDS value will be accessible
through RTCVALH and RTCVALL until the pointer
value is manually changed.
TABLE 19-1: RTCVAL REGISTER MAPPING
RTCPTR
<1:0>
RTCC Value Register Window
RTCVAL<15:8> RTCVAL<7:0>
00
MINUTES
SECONDS
01
WEEKDAY
HOURS
10
MONTH
DAY
11
—
YEAR
The Alarm Value register window (ALRMVALH and
ALRMVALL) uses the ALRMPTR bits
(ALCFGRPT<9:8>) to select the desired Alarm register
pair (see Table 19-2).
By writing the ALRMVALH byte, the Alarm Pointer
value, ALRMPTR<1:0>, decrements by one until it
reaches ‘00’. Once it reaches ‘00’, the ALRMMIN and
ALRMSEC value will be accessible through
ALRMVALH and ALRMVALL until the pointer value is
manually changed.
TABLE 19-2: ALRMVAL REGISTER
MAPPING
ALRMPTR
Alarm Value Register Window
<1:0>
ALRMVAL<15:8> ALRMVAL<7:0>
00
ALRMMIN
ALRMSEC
01
ALRMWD
ALRMHR
10
ALRMMNTH
ALRMDAY
11
—
—
Considering that the 16-bit core does not distinguish
between 8-bit and 16-bit read operations, the user must
be aware that when reading either the ALRMVALH or
ALRMVALL bytes it will decrement the ALRMPTR<1:0>
value. The same applies to the RTCVALH or RTCVALL
bytes with the RTCPTR<1:0> being decremented.
Note: This only applies to read operations and
not write operations.
19.1.2 WRITE LOCK
In order to perform a write to any of the RTCC Timer
registers, the RTCWREN bit (RCFGCAL<13>) must be
set (refer to Example 19-1).
EXAMPLE 19-1: SETTING THE RTCWREN BIT IN MPLAB^® C30
asm volatile("disi #13");
asm volatile("push W1");
asm volatile("push W2");
asm volatile("push W3");
asm volatile("MOV #NVMKEY, W1");
//move the address of NVMKEY into W1
asm volatile("MOV #0x55, W2");
asm volatile("MOV #0xAA, W3");
asm volatile("MOV W2, [W1]");
//start 55/AA sequence
NOP(); //There must be an instruction between the two writes ( either a NOP or a MOV to W)
asm volatile("MOV W3, [W1]");
asm volatile("BSET RCFGCAL, #13");
//set the RTCWREN bit
asm volatile("pop W3");
asm volatile("pop W2");
asm volatile("pop W1");
Note:
To avoid accidental writes to the timer, it is recommended that the RTCWREN bit (RCFGCAL<13>) is kept
clear at any other time. For the RTCWREN bit to be set, there is only 1 instruction cycle time window allowed
between the 55h/AA sequence and the setting of RTCWREN; therefore, it is recommended that the code in
Example 19-1 be followed.
DS39747F-page 164
 2005-2012 Microchip Technology Inc.