PIC24FJ128GA010_12 Datasheet, PDF (130/258 Pages) Microchip Technology – 64/80/100-Pin, General Purpose, 16-Bit Flash Microcontrollers

PIC24FJ128GA010 FAMILY
REGISTER 15-1: SPIxSTAT: SPIx STATUS AND CONTROL REGISTER
R/W-0
SPIEN
bit 15
U-0
R/W-0
U-0
—
SPISIDL
—
U-0
R-0
—
SPIBEC2
R-0
SPIBEC1
R-0
SPIBEC0
bit 8
R/W-0
SRMPT
bit 7
R/C-0
SPIROV
R/W-0
SRXMPT
R/W-0
SISEL2
R/W-0
SISEL1
R/W-0
SISEL0
R-0
SPITBF
R-0
SPIRBF
bit 0
Legend:
R = Readable bit
-n = Value at POR
C = Clearable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
bit 14
bit 13
bit 12-11
bit 10-8
bit 7
bit 6
bit 5
bit 4-2
SPIEN: SPIx Enable bit
1 = Enables module and configures SCKx, SDOx, SDIx and SSx as serial port pins
0 = Disables module
Unimplemented: Read as ‘0’
SPISIDL: Stop in Idle Mode bit
1 = Discontinues module operation when device enters Idle mode
0 = Continues module operation in Idle mode
Unimplemented: Read as ‘0’
SPIBEC<2:0>: SPIx Buffer Element Count bits
Master mode:
Number of SPI transfers pending.
Slave mode:
Number of SPI transfers unread.
SRMPT: Shift Register (SPIxSR) Empty bit (valid in Enhanced Buffer mode)
1 = SPIx Shift register is empty and ready to send or receive
0 = SPIx Shift register is not empty; read as ‘0’
SPIROV: Receive Overflow Flag bit
1 = A new byte/word is completely received and discarded; the user software has not read the previous
data in the SPIxBUF register
0 = No overflow has occurred
SRXMPT: Receive FIFO Empty bit (valid in Enhanced Buffer mode)
1 = Receive FIFO is empty
0 = Receive FIFO is not empty’
SISEL<2:0>: SPIx Buffer Interrupt Mode bits (valid in Enhanced Buffer mode)
111 = Interrupt when the SPIx transmit buffer is full (SPITBF bit is set)
110 = Interrupt when the last bit is shifted into SPIxSR, as a result, the TX FIFO is empty
101 = Interrupt when the last bit is shifted out of SPIxSR, now the transmit is complete
100 = Interrupt when one data is shifted into the SPIxSR, as a result, the TX FIFO has one open spot
011 = Interrupt when the SPIx receive buffer is full (SPIRBF bit is set)
010 = Interrupt when the SPIx receive buffer is 3/4 or more full
001 = Interrupt when data is available in the receive buffer (SRMPT bit is set)
000 = Interrupt when the last data in the receive buffer is read, and as a result, the buffer is empty
(SRXMPT bit set)
DS39747F-page 130
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