PIC24FJ128GA010_12 Datasheet, PDF (125/258 Pages) Microchip Technology – 64/80/100-Pin, General Purpose, 16-Bit Flash Microcontrollers

PIC24FJ128GA010 FAMILY
REGISTER 14-1: OCxCON: OUTPUT COMPARE x CONTROL REGISTER
U-0
U-0
R/W-0
U-0
U-0
U-0
U-0
—
—
OCSIDL
—
—
—
—
bit 15
U-0
—
bit 8
U-0
—
bit 7
U-0
U-0
R-0, HC
R/W-0
R/W-0
R/W-0
R/W-0
—
—
OCFLT⁽¹⁾ OCTSEL⁽¹⁾
OCM2
OCM1
OCM0
bit 0
Legend:
R = Readable bit
-n = Value at POR
HC = Hardware Clearable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-14
bit 13
bit 12-5
bit 4
bit 3
bit 2-0
Unimplemented: Read as ‘0’
OCSIDL: Stop Output Compare x Module Stop in Idle Control bit
1 = Output capture x will halt in CPU Idle mode
0 = Output capture x will continue to operate in CPU Idle mode
Unimplemented: Read as ‘0’
OCFLT: PWM Fault Condition Status bit⁽¹⁾
1 = PWM Fault condition has occurred (cleared in HW only)
0 = No PWM Fault condition has occurred (this bit is only used when OCM<2:0> = 111)
OCTSEL: Output Compare x Timer Select bit⁽¹⁾
1 = Timer3 is the clock source for output Compare x
0 = Timer2 is the clock source for output Compare x
OCM<2:0>: Output Compare x Mode Select bits
111 = PWM mode on OCx, Fault pin is enabled⁽²⁾
110 = PWM mode on OCx, Fault pin is disabled⁽²⁾
101 = Initialize the OCx pin low, generate continuous output pulses on the OCx pin
100 = Initialize the OCx pin low, generate single output pulse on the OCx pin
011 = Compare event toggles OCx pin
010 = Initialize the OCx pin high, a compare event forces the OCx pin low
001 = Initialize the OCx pin low, a compare event forces the OCx pin high
000 = Output compare channel is disabled
Note 1: Refer to the device data sheet for specific time bases available to the output compare module.
2: The OCFA pin controls the OC1-OC4 channels; OCFB pin controls the OC5 channel.
 2005-2012 Microchip Technology Inc.
DS39747F-page 125