PIC24FJ128GA010_12 Datasheet, PDF (140/258 Pages) Microchip Technology – 64/80/100-Pin, General Purpose, 16-Bit Flash Microcontrollers

PIC24FJ128GA010 FAMILY
REGISTER 16-1: I2CxCON: I2Cx CONTROL REGISTER
R/W-0
I2CEN
bit 15
U-0
R/W-0
R/W-1, HC
R/W-0
—
I2CSIDL
SCLREL
IPMIEN
R/W-0
A10M
R/W-0
DISSLW
R/W-0
SMEN
bit 8
R/W-0
GCEN
bit 7
R/W-0
STREN
R/W-0
ACKDT
R/W-0, HC R/W-0, HC
ACKEN
RCEN
R/W-0, HC
PEN
R/W-0, HC
RSEN
R/W-0, HC
SEN
bit 0
Legend:
R = Readable bit
-n = Value at POR
HC = Hardware Clearable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8
bit 7
bit 6
I2CEN: I2Cx Enable bit
1 = Enables the I2Cx module and configures the SDAx and SCLx pins as serial port pins
0 = Disables I2Cx module; all I²C™ pins are controlled by port functions
Unimplemented: Read as ‘0’
I2CSIDL: Stop in Idle Mode bit
1 = Discontinues module operation when the device enters an Idle mode
0 = Continues module operation in Idle mode
SCLREL: SCLx Release Control bit (when operating as an I²C™ slave)
1 = Releases SCLx clock
0 = Holds SCLx clock low (clock stretch)
If STREN = 1:
Bit is R/W (i.e., software may write ‘0’ to initiate stretch and write ‘1’ to release clock). Hardware is clear
at the beginning of slave transmission. Hardware is clear at the end of slave reception.
If STREN = 0:
Bit is R/S (i.e., software may only write ‘1’ to release clock). Hardware is clear at the beginning of slave
transmission.
IPMIEN: Intelligent Peripheral Management Interface (IPMI) Enable bit
1 = IPMI Support mode is enabled; all addresses are Acknowledged
0 = IPMI mode is disabled
A10M: 10-Bit Slave Address bit
1 = I2CxADD is a 10-bit slave address
0 = I2CxADD is a 7-bit slave address
DISSLW: Disable Slew Rate Control bit
1 = Slew rate control is disabled
0 = Slew rate control is enabled
SMEN: SMBus Input Levels bit
1 = Enables I/O pin thresholds compliant with the SMBus specification
0 = Disables SMBus input thresholds
GCEN: General Call Enable bit (when operating as an I²C slave)
1 = Enables interrupt when a general call address is received in the I2CxRSR (module is enabled for
reception)
0 = General call address is disabled
STREN: SCLx Clock Stretch Enable bit (when operating as an I²C slave)
Used in conjunction with the SCLREL bit.
1 = Enables software or receives clock stretching
0 = Disables software or receives clock stretching
DS39747F-page 140
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