MA015 Datasheet, PDF (29/29 Pages) Megawin Technology Co., Ltd – Build-in watchdog timer

MA015 Datasheet
Version 2.00
Compare the major difference with MLC041
Added:
1. Low Voltage Detector in 1.9V.
2. Low Voltage Protector in 0.9V to V_LVR (Low voltage reset voltage). In LVP state, oscillator is stopped by logic
circuit; oscillator will start again when V_DD > V_LVR.
3. Reset OK function, this function is mask option.
4. Port 3.0 ~ Port 3.6 with interrupt function. Interrupt function setting is individual.
5. Added Port 3.0 ~ Port 3.6 for GPIO, Port 3.6 can be the clock source of timer.
Deleted:
1. NMI selects function.
2. Divider 0 and Divider 1 control SFR and interrupt function.
3. AGND, AV_DD, SPK1, SPK2, TEST and 32K Crystal Pad (X32I / X32O).
4. F_CPU selector.
5. CH1, CH2, CH3 three DAC buffer and control SFR
6. Voice / Tone control SFR
Modify:
1. Add RAM from 256 Bytes to 320 Bytes.
2. Modify Memory Map, Extended share memory from 0x0000h~0x007FH to 0x0000h~0x00BFh.
3. Move all SFR to zero page (0x00C0H ~ 0x00FFH) and modify the addresses of SFR.
4. Modify the interrupt vector (Port 0 and Port 3 share the “Port” interrupt vector)
5. Interrupt vector table: Delete NMI, Divider 0 and Divider 1. Modify Port 0 to Port.
6. IRQ: Delete Divider 0 and Divider 1. Added LVD. Modify Port 0 to Port.
7. Divider is only used to generate clock to Timer and WDT.
8. Power saving controls SFR: Delete X32 relation function (because there is no X32 pad).
9. Release halt mode SFR: Delete Divider 0, Divider 1. Modify Port 0 to Port.
10. Port 0.0 ~ 0.7 and Port 3.0~ 3.6 with interrupt function. Interrupt function setting is individual.
11. Port 1 multi-function selector. Keep Port 1.3, P1.6 and P1.7 can be timer 0, timer 1 and timer 2 carry out.
Delete Port1.4 and P1.5 timer serial input.
12. Timer 0: Modify clock source; Delete Shift control and serial input through P1.4 and P1.5; Keep carry out with
P1.3.
13. Timer 1: Modify clock source; Delete Shift control and serial input through /P1.4; Keep carry out with P1.6.
14. Timer 2: Modify clock source; Keep carry out with P1.7.
15. Delete I/O weak input pull high resistor (keep 50K  pull-high).
16. Change Port 0, P1.4~P1.7, Port 2 and Port 3 drive current from 1.5mA to 3.0mA.
17. Change P1.0~P1.3 drive current from 1.5mA to 10.0mA.
18. Change Port 0, Port 1, Port 2 and Port 3 sink current from 9.0mA to 6.0mA.
19. Change WDT time to 4 steps: 65.5ms, 131ms, 262ms and 524ms.
This document information is the intellectual property of Megawin Technology.
 Megawin Technology Co., Ltd. 2011 All right reserved.
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