MA015 Datasheet, PDF (20/29 Pages) Megawin Technology Co., Ltd – Build-in watchdog timer

MA015 Datasheet
Version 2.00
12 Configurable I/O Ports
12.1 Port 0
Address
Name
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 _{Bit 0} R W
00E0H
P0
P07 P06 P05 P04 P03 P02 P01 P00  
00E1H
P0CR
CP07 CP06 CP05 CP04 CP03 CP02 CP01 CP00  
00E2H
P0MR
-
- MP05 MP04 -
-
MP01 MP00  
00E3H
P0IEN
IE7 IE6 IE5 IE4 IE3 IE2 IE1 IE0  
Port 0 is an 8-bit I/O port; each pin can be programmed as input or output individually.
P0CR: P0.0 ~ P0.7 is input or output. 0: input, 1: output
P0MR: P0.0 ~ P0.7, pull-high and CMOS/NMOS setting
P0MR.0: P0.0 ~ P0.3 Pull-high control, 0: disable, 1:enable
P0MR.1: P0.0 ~ P0.3 CMOS/NMOS selector, 0: CMOS, 1:NMOS
P0MR.4: P0.4 ~ P0.7 Pull-high control, 0: disable, 1: enable
P0MR.5: P0.4 ~ P0.7 CMOS/NMOS selector, 0: CMOS, 1:NMOS
P0IEN: P0.0 ~ P0.7 interrupt enable, 0:disable, 1:enable
At initial reset, the Port 0 is all in input mode. Each pin of Port 0 can be specified as input or output mode
independently by the P0CR registers. When Port 0 is used as output port, CMOS or NMOS open drain output type
can be selected by the P0MR register. Port 0 has the internal pull-high resistors that can be enabled/disabled by
specifying the P0MR.0 and P0MR.4 respectively. The pull-high resistors will be temporarily disable if the port is
specified as output mode. The read value will be the output buffer status in output mode. When Port 0 is used
as input mode, P0IEN (is set to enable), the RLH_EN, and IRQ_EN corresponding to the Port 0 are set, a signal
change at the Port 0 (any pin) will execute the halt mode release or interrupt subroutine. Both the raising or falling
signal will set the Port 0 event. The Schmitt trigger circuit is added in the input port part of all I/O pins.
Please set Port 0 as output high before set it as input mode, if speeds up the internal pull-high effect is needed. If
the I/O ports are not used in your application, please set them as input with pull-high or output mode to avoid
unnecessary power consumption.
Input/Output Pin of the P0 _Vd
P0MR.
d
1
Output
Buffer
Enable
DAT
A
BUS
Enable
STA
P0CR.x
P0,#data
Instruction
P0MR.0
I/O
PIN
P0.n
LVR
Enable
LDA buffer,
P0
Instruction
This document information is the intellectual property of Megawin Technology.
 Megawin Technology Co., Ltd. 2011 All right reserved.
QP-7300-03D
20/29