MA015 Datasheet, PDF (22/29 Pages) Megawin Technology Co., Ltd – Build-in watchdog timer

MA015 Datasheet
Version 2.00
12.4 Port 3
Port 3
Address
Name
Bit 7 Bit 6 Bit 5 Bit 4
00ECH
P3
-
P36 P35 P34
00EDH
P3CR
-
CP36 CP35 CP34
00EEH
P3MR
-
- MP35 MP34
00EFH
P3IEN
-
IE6 IE5 IE4
Port 3 is a 7-bit I/O port; refer to port 0 for more information.
P3CR: P3.0 ~ P3.6 are input or output. 0: input, 1: output
P3MR: P3.0 ~ P3.6, pull-high and CMOS/NMOS setting
P3MR.0: P3.0 ~ P3.3 Pull-high control, 0: disable, 1:enable
P3MR.1: P3.0 ~ P3.3 CMOS/NMOS selector, 0: CMOS, 1:NMOS
P3MR.4: P3.4 ~ P3.6 Pull-high controls, 0: disable, 1: enable
P3MR.5: P3.4 ~ P3.6 CMOS/NMOS selector, 0: CMOS, 1:NMOS
Bit 3
P33
CP33
-
IE3
Bit 2
P32
CP32
-
IE2
Bit 1
P31
CP31
MP31
IE1
Bit 0
P30
CP30
MP30
IE0
RW




P3IEN: P3.0~P3.6 interrupt enable, 0:disable, 1:enable
When Port 3 is used as input mode, P3IEN (is set to enable), the RLH_EN, and IRQ_EN corresponding to the Port
3 are set, a signal change at the Port 3 (any pin) will execute the halt mode release or interrupt subroutine. Both
the raising or falling signal will set the Port event. The Schmitt trigger circuit is added in the input port part of all I/O
pins.
Please set Port 3 as output high before set it as input mode, if a speed up the internal pull-high effect is needed. If
the I/O ports are not used in your application, please set them as input with pull-high or output mode to avoid
unnecessary power consumption.
This document information is the intellectual property of Megawin Technology.
 Megawin Technology Co., Ltd. 2011 All right reserved.
QP-7300-03D
22/29