MA015 Datasheet, PDF (17/29 Pages) Megawin Technology Co., Ltd – Build-in watchdog timer

MA015 Datasheet
Version 2.00
11 Timer
11.1 Timer0
Timer0
Address
Name
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 _{Bit 0} R W
00C8H
TM0L
T7
T6
T5
T4
T3
T2
T1
T0  
00C9H
TM0H
T15 T14 T13 T12 T11 T10 T9
T8  
00CAH
TM0_CTL STC RL/S TKES
-
-
TKI2 TKI1 TKI0  
Timer 0 is a 16-bit down-count counter. The counter underflow frequency of Timer 0 can be calculated with the equation:
F_{TM0_UV} = F_TM0 / (TM0+1)
STC: Start/Stop counting. 1: start and pre-load the value to counter, 0: stop timer clock (set this bit to 1 will be ignored when this
bit already set to 1)
RL/S: Auto-reload disable/enable. 1: disable auto-reload, 0: enable auto-reload
TKES: Event or series input clock-in trigger edge selector; 0: rising edge, 1: falling edge
TKI2
0
0
0
0
1
TKI1
0
0
1
1
0
TKI0
0
1
0
1
0
Selected TM0 input clock source
FOSC / 1
FOSC / 2
FOSC / 4
FOSC / 8
P3.6
Fosc / 1
Fosc / 2
Fosc / 4
Fosc / 8
P3.6
MUX
TM0_CTL.STC
TM0_CTL.TKI2
TM0_CTL.TKI1
TM0_CTL.TKI0
TM0L re-load buffer (W)
reload
TM0H re-load buffer (W)
TM0L (R)
TM0
TM0H (R)
reload
Control
Logic
TM0_CTL.6
TM0_CTL.7
TM0_UV
/2
P1_MFR.6
TM0
Underflow
P1.3
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 Megawin Technology Co., Ltd. 2011 All right reserved.
QP-7300-03D
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