MA015 Datasheet, PDF (12/29 Pages) Megawin Technology Co., Ltd – Build-in watchdog timer

MA015 Datasheet
Version 2.00
8 Interrupt
There are four kinds of interrupt sources are provided in MA015. The flag IRQ_EN and IRQ_ST are used to control
the interrupts. When flag IRQ_ST is set to ‘1’ by hardware and the corresponding bits of flag IRQ_EN has been set
by software, an interrupt is generated. When an interrupt occurs, all of the interrupts are inhibited until the CLI or
STA IRQ_EN, #I instruction is invoked. Executing the SEI instruction can also disable the interrupts.
Vector Address
FFFEH, FFFFH
FFFCH, FFFDH
FFFCH, FFFDH
FFFCH, FFFDH
FFFCH, FFFDH
FFFCH, FFFDH
FFFAH, FFFBH
FFF8H, FFF9H
FFF6H, FFF7H
FFF4H, FFF5H
FFF2H, FFF3H
FFF1H, FFF0H
Item
-
PAD RESET
LVR
POR
WDT
RESET OK
-
-
TM0
Port
TM1
TM2
Table 8-1 Interrupt Vector Table
Priority _Properties
Memo
-
-
Reserve
1
Ext.
Initial reset
1
Int.
Initial reset
1
Int.
Initial reset
1
Int.
Initial reset
1
Int.
Initial reset
-
-
Reserve
-
-
Reserve
2
Int.
Timer 0 overflow interrupt
3
Ext.
Port P0, P3 interrupt vector
4
Int.
Timer 1 overflow interrupt
5
Int.
Timer 2 overflow interrupt
8.1 Interrupt Register
IRQ enable flag
Address
Name
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2
00C0H
IRQ_EN
-
-
-
TM2 TM1 Port
Program can enable or disable the ability of triggering IRQ through this register.
0: Disable (default "0" at initialization)
1: Enable
Port: Raising or falling edge occurs at port 0 (or port 3) input mode.
TM0, TM1, TM2: Timer 0/1/2 underflow
Bit 1
TM0
Bit 0 R W
-
-
IRQ status flag
Address
Name
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1
00C1H
IRQ_ST
-
-
-
TM2 TM1 Port TM0
When IRQ occurs, program can read this register to know which source triggering IRQ.
Bit 0 R W
LVD  -
LVD flag:
The Low Voltage Detector has no de-bounce ability. When V_DD is equal or lower than the condition of LVD, the LVD flag will be
set to high immediately. De-bounce could be implement by firmware. The LVD flag has not interrupt ability and set by hardware.
When V_DD is higher than the condition of LVD, the LVD flag will be clear by hardware.
IRQ clear flag
Address
Name
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
00C1H IRQ_CLR
-
-
-
TM2 TM1 Port TM0 LVD
Program can clear the interrupt event by writing ‘1’ into the corresponding bit (except LVD bit).
RW
-
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 Megawin Technology Co., Ltd. 2011 All right reserved.
QP-7300-03D
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