MA015 Datasheet, PDF(14/29 Page) Megawin Technology Co., Ltd

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MA015 Datasheet, PDF (14/29 Pages) Megawin Technology Co., Ltd – Build-in watchdog timer

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MA015 Datasheet

Version 2.00

9 Reset

9.1 Low Voltage Reset (LVR)

The MA015 provides low voltage reset circuit in order to monitor the supply voltage of the device. If the supply

voltage of the device is within the range of 0.9V ~ VLVR (such as changing the battery), the LVR will automatically

reset the device internally.

In the LVR active period, the on-chip oscillator is stopped. All I/O port will be set as input tri-state mode and the

leakage current will below 0.1 ïA. If an external capacitor (example: 47ïF) is connected between VDD and GND in

this condition, the contents of on-chip RAM will be kept.

9.2 Watchdog Timer (WDT)

Address

Name

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R W

RSTS -

ï-

00C4H

WDT_CTL CLR

RSEL CKI1 CKI0 - ï

RSTS: WDT reset status, set by hardware when WDT overflows and clear by hardware reset or set WDT_CLR.7 to one (this bit

is read only)

RSEL: WDT reset selector, = 0 Reset whole chip except RSTS (WDT_CTL.7)

= 1 Reset PC and IRQ_EN only

CKI1, CKI0: WDT clock selector, = 00 Fosc / (131072*16) selected (1.90Hz = 526ms @ Fosc = 4MHz )

= 01 Fosc / (65536*16) selected (3.81Hz = 262ms @ Fosc = 4MHz )

= 10 Fosc / (32768*16) selected (7.63Hz = 131ms @ Fosc = 4MHz )

= 11 Fosc / (16384*16) selected (15.26Hz = 65.5ms @ Fosc = 4MHz)

CLR: RSTS clear control bit, program can clear RSTS by program "1" into this bit (this bit is write only)

The watchdog timer (WDT), which is organized as a 4-bit counter, is designed to prevent the program from

unknown errors. The WDT is enabling by code option. If the WDT overflows, the WDT reset function will be

performed. The watchdog timer control register (WDT_CTL) controls the WDT reset function. RSTS (WDT_CTL.7)

is set by hardware when the WDT overflows and is cleared by store one to the bit 7 of WDT_CLR register or

hardware reset. There are two types of WDT reset, which is selected by RSEL (bit2 of WDT_CTL). WDT overflow

will cause two types reset depending on the setting of RSEL ï¾ if RSEL is equal to 0, the reset is the same as

hardware reset except the setting of WDT_CTL and WDT_CLR; If RSEL is equal to 1, the reset only acts on

program counter (PC) and IRQ_EN. The WDT clock frequency is decided by bit1 and bit0 of WDT_CTL register.

Store one to the bit 7 of WDT_CLR register will also reset the contents of the WDT. In normal operation, the

application program must reset WDT before it overflows. The organization of the divider1 and watchdog timer is

shown as below.

WDT_CTL.0

WDT_CTL.1

Fosc/16384

Fosc/32768

Fosc/65536

Fosc/131072

(Option code = 0)

Disable

Enable

WDT

Qw1 Qw2 Qw3 Qw4

WDT_CTL.2

Overflow signal

System Reset

except WDT_CTL.7

PC & IRQ_EN reset

(other peripheral unchanged)

(Option code = 1)

WDT_CTL.7

Fosc

Q0 Q1 ... Q13 Q14 Q15 Q16

Divider

Figure 9-1 Watch Dog Diagram

Hardware reset

WDT_CLR <- 8XH

This document information is the intellectual property of Megawin Technology.

QP-7300-03D

14/29

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