MA015 Datasheet, PDF (19/29 Pages) Megawin Technology Co., Ltd – Build-in watchdog timer

MA015 Datasheet
Version 2.00
11.3 Timer2
Timer2
Address
Name
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 _{Bit 0} R W
00D0H
TM2L
T7
T6
T5
T4
T3
T2
T1
T0  
00D1H
TM2H
T15 T14 T13 T12 T11 T10 T9
T8  
00D2H
TM2_CTL STC RL/S TKES -
-
TKI2 TKI1 TKI0  
Timer 2 is a 16-bit down-count counter. The counter underflow frequency of timer 2 can be calculated with the equation:
F_{TM2_UV} = F_TM2 / (TM2+1)
STC: Start/Stop counting. 1: start and pre-load the value to counter, 0: stop timer clock
RL/S: Auto-reload disable/enable. 1: disable auto-reload, 0: enable auto-reload
TKES: Event or series input clock-in trigger edge selector; 0: rising edge, 1: falling edge
TKI2
0
0
0
0
1
TKI1
0
0
1
1
0
TKI0
0
1
0
1
0
Selected TM1 input clock source
FOSC / 1
FOSC / 2
FOSC / 4
FOSC / 8
P3.6
Fosc / 1
Fosc / 2
Fosc / 4
Fosc / 8
P3.6
MUX
TM2_CTL.STC
TM2_CTL.TKI2
TM2_CTL.TKI1
TM2_CTL.TKI0
TM2L re-load buffer (W)
reload
TM2L (R)
TM2
TM2H re-load buffer (W)
TM2H (R)
reload
Control
Logic
TM2_CTL.6
TM2_CTL.7
TM2_UV
/2
P1_MFR.7
TM2
Underflow
P1.7
For example: (if Fosc = 4.096MHz)
TM2
00 00H
00 01H
00 02H
…
00 FFH
…
FF FFH
Frequency
Invalid
2.048MHz
1.365MHz
…
16KHz
…
62.5Hz
This document information is the intellectual property of Megawin Technology.
 Megawin Technology Co., Ltd. 2011 All right reserved.
QP-7300-03D
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