MA015 Datasheet, PDF (16/29 Pages) Megawin Technology Co., Ltd – Build-in watchdog timer

MA015 Datasheet
Version 2.00
10 Power Control
10.1 Power Control Register
Power saving control
Address
Name
00C5H
PWR_CR
Bit 7
-
Bit 6
-
Bit 5
-
Bit 4
-
Bit 3
-
Bit 2 Bit 1 _{Bit 0} R W
- CKC0 HALT - 
CKC0
0
1
System clock control
FOSC enable, (Normal mode)
FOSC disable, (Stop mode)
HALT: FCPU off-line control bit. 1: FCPU off-line, 0: FCPU on-line
Program can switch the normal operation mode to the power-saving mode for saving power consumption through
this register. There are two power saving modes in this system.
Stop mode: (PWR_CR.CKC0 = 1)
All system clocks stop oscillating. The uC can be awakened from stop mode by 3-ways: Port interrupt, hardware
reset, or power-on reset.
Halt mode: (PWR_CR.HALT = 1)
The FCPU clock in off-line status. The oscillator still oscillating if the PWR_CR.CKC0 keep low. The uC can be
awakened from halt mode by 3-ways: all interrupt events (Timer 0, Timer 1, Timer 2, Port), hardware reset, or
power-on reset.
Release halt mode enable flag
Address
Name
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 _{Bit 0} R W
00C6H
RLH_EN
-
-
-
TM2 TM1 Port TM0
-
-
Set IRQ_CLR register to clear the halt release event.
Release halt status flag is the IRQ_ST register.
This document information is the intellectual property of Megawin Technology.
 Megawin Technology Co., Ltd. 2011 All right reserved.
QP-7300-03D
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