MT41J256M4 Datasheet, PDF (75/181 Pages) Micon Design Technology Corporation – 1Gb: x4, x8, x16 DDR3 SDRAM

1Gb: x4, x8, x16 DDR3 SDRAM
Speed Bin Tables
17. The cumulative jitter error (^tERRnPER), where n is the number of clocks between 2 and
50, is the amount of clock time allowed to accumulate consecutively away from the
average clock over n number of clock cycles.
18. ^tDS (base) and ^tDH (base) values are for a single-ended 1 V/ns DQ slew rate and
2 V/ns differential DQS, DQS# slew rate.
19. These parameters are measured from a data signal (DM, DQ0, DQ1, and so forth)
transition edge to its respective data strobe signal (DQS, DQS#) crossing.
20. The setup and hold times are listed converting the base specification values (to which
derating tables apply) to VREF when the slew rate is 1 V/ns. These values, with a slew
rate of 1 V/ns, are for reference only.
21. Special setup and hold derating and different ^tVAC numbers apply when using 150mV
AC threshold.
22. When the device is operated with input clock jitter, this parameter needs to be der-
ated by the actual ^tJITPER of the input clock (output deratings are relative to the
SDRAM input clock).
23. Single-ended signal parameter.
24. The DRAM output timing is aligned to the nominal or average clock. Most output
parameters must be derated by the actual jitter error when input clock jitter is
present, even when within specification. This results in each parameter becoming
larger. The following parameters are required to be derated by subtracting
t_{ERR10PER (MAX):} t_{DQSCK (MIN),} t_{LZ (DQS) MIN,} t_{LZ (DQ) MIN, and} t_{AON (MIN).}
The following parameters are required to be derated by subtracting ^tERR_10PER (MIN):
t_{DQSCK (MAX),} t_{HZ (MAX),} t_{LZ (DQS) MAX,} t_{LZ (DQ) MAX, and} t_{AON (MAX). The}
parameter ^tRPRE (MIN) is derated by subtracting ^tJITPER (MAX), while ^tRPRE (MAX) is
derated by subtracting ^tJITPER (MIN).
25. The maximum preamble is bound by ^tLZDQS (MAX).
26. These parameters are measured from a data strobe signal (DQS, DQS#) crossing to its
respective clock signal (CK, CK#) crossing. The specification values are not affected by
the amount of clock jitter applied, as these are relative to the clock signal crossing.
These parameters should be met whether clock jitter is present.
27. The ^tDQSCK DLL_DIS parameter begins CL + AL - 1 cycles after the READ command.
28. The maximum postamble is bound by ^tHZDQS (MAX).
29. Commands requiring a locked DLL are: READ (and RDAP) and synchronous ODT
commands. In addition, after any change of latency ^tXPDLL, timing must be met.
30. ^tIS (base) and ^tIH (base) values are for a single-ended 1 V/ns control/command/
address slew rate and 2 V/ns CK, CK# differential slew rate.
31. These parameters are measured from a command/address signal transition edge to
its respective clock (CK, CK#) signal crossing. The specification values are not affected
by the amount of clock jitter applied as the setup and hold times are relative to the
clock signal crossing that latches the command/address. These parameters should be
met whether clock jitter is present.
32. For these parameters, the DDR3 SDRAM device supports ^tnPARAM (nCK) =
RU(^tPARAM [ns]/^tCK[AVG] [ns]), assuming all input clock jitter specifications are sat-
isfied. For example, the device will support ^tnRP (nCK) = RU(^tRP/^tCK[AVG]) if all
input clock jitter specifications are met. This means for DDR3-800 6-6-6, of which
t_{RP = 15ns, the device will support} t_{nRP = RU(}t_RP/t_{CK[AVG]) = 6 as long as the input}
clock jitter specifications are met. That is, the PRECHARGE command at T0 and the
ACTIVATE command at T0 + 6 are valid even if six clocks are less than 15ns due to
input clock jitter.
33. During READs and WRITEs with auto precharge, the DDR3 SDRAM will hold off the
internal PRECHARGE command until ^tRAS (MIN) has been satisfied.
PDF: 09005aef826aa906/Source: 09005aef82a357c3
1Gb_DDR3_3.fm - Rev. D 8/1/08 EN
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