MT41J256M4 Datasheet, PDF (63/181 Pages) Micon Design Technology Corporation – 1Gb: x4, x8, x16 DDR3 SDRAM

1Gb: x4, x8, x16 DDR3 SDRAM
Speed Bin Tables
Speed Bin Tables
Table 49: DDR3-800 Speed Bins
DDR3-800 Speed Bin
CL-^tRCD-^tRP
-25E
5-5-5
-25
6-6-6
Parameter
ACTIVATE to internal READ or WRITE delay
time
PRECHARGE command period
ACTIVATE-to-ACTIVATE or REFRESH
command period
ACTIVATE-to-PRECHARGE command period
CL = 5
CWL = 5
CL = 6
CWL = 5
Supported CL settings
Supported CWL settings
Symbol
t_RCD
t_RP
t_RC
t_RAS
t_{CK (AVG)}
t_{CK (AVG)}
Min
12.5
Max
–
12.5
–
50
–
37.5 9 × ^tREFI
2.5
3.3
2.5
3.3
5, 6
5
Min
15
Max
–
Units Notes
ns
15
–
ns
52.5
–
ns
37.5 9 × ^tREFI ns
1
Reserved
ns
2, 3
2.5
3.3
ns
2
6
CK
5
CK
Notes:
1. ^tREFI depends on T_OPER.
2. The CL and CWL settings result in ^tCK requirements. When making a selection of ^tCK, both
CL and CWL requirement settings need to be fulfilled.
3. Reserved settings are not allowed.
PDF: 09005aef826aa906/Source: 09005aef82a357c3
1Gb_DDR3_3.fm - Rev. D 8/1/08 EN
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