MT41J256M4 Datasheet, PDF (127/181 Pages) Micon Design Technology Corporation – 1Gb: x4, x8, x16 DDR3 SDRAM

1Gb: x4, x8, x16 DDR3 SDRAM
Operations
DDR3 SDRAM need a longer time to calibrate RON and ODT at power-up initialization
and self refresh exit and a relatively shorter time to perform periodic calibrations. DDR3
SDRAM defines two ZQ CALIBRATION commands: ZQ CALIBRATION LONG (ZQCL)
and ZQ CALIBRATION SHORT (ZQCS). An example of ZQ calibration timing is shown in
Figure 66.
All banks must be precharged and ^tRP must be met before ZQCL or ZQCS commands
can be issued to the DRAM. No other activities (other than another ZQCL or ZQCS
command may be issued to another DRAM) can be performed on the DRAM channel by
the controller for the duration of ^tZQINIT or ^tZQOPER . The quiet time on the DRAM
channel helps accurately calibrate RON and ODT. After DRAM calibration is achieved,
the DRAM should disable the ZQ ball’s current consumption path to reduce power.
ZQ CALIBRATION commands can be issued in parallel to DLL RESET and locking time.
Upon self refresh exit, an explicit ZQCL is required if ZQ calibration is desired.
In dual-rank systems that share the ZQ resistor between devices, the controller must not
allow overlap of ^tZQINIT, ^tZQOPER, or ^tZQCS between ranks.
Figure 66: ZQ Calibration Timing (ZQCL and ZQCS)
CK#
T0
CK
Command ZQCL
Address
A10
CKE 1
ODT 2
DQ 3
T1
Ta0
Ta1
NOP
NOP
NOP
High-Z
tZQ_{INIT or} tZQ_OPER
Ta2
Ta3
Tb0
Tb1
Tc0
Tc1
Valid
Valid
ZQCS
Valid
Valid
Valid
Valid
Valid
Valid
1
Valid
Valid
2
Activities
3
NOP
NOP
NOP
High-Z
tZQ_CS
Tc2
Valid
Valid
Valid
Valid
Valid
Activ-
ities
ACTIVATE
Indicates A Break in
Time Scale
Don’t Care
Notes:
1. CKE must be continuously registered HIGH during the calibration procedure.
2. ODT must be disabled via the ODT signal or the MRS during the calibration procedure.
3. All devices connected to the DQ bus should be High-Z during calibration.
Before any READ or WRITE commands can be issued to a bank within the DRAM, a row
in that bank must be opened (activated). This is accomplished via the ACTIVATE
command, which selects both the bank and the row to be activated.
After a row is opened with an ACTIVATE command, a READ or WRITE command may be
issued to that row, subject to the ^tRCD specification. However, if the additive latency is
programmed correctly, a READ or WRITE command may be issued prior to ^tRCD (MIN).
In this operation, the DRAM enables a READ or WRITE command to be issued after the
ACTIVATE command for that bank, but prior to ^tRCD (MIN) with the requirement that
(ACTIVATE-to-READ/WRITE) + AL ≥ ^tRCD (MIN) (see "POSTED CAS ADDITIVE Latency
(AL)" on page 115). ^tRCD (MIN) should be divided by the clock period and rounded up
PDF: 09005aef826aa906/Source: 09005aef82a357c3
1Gb_DDR3_4.fm - Rev. D 8/1/08 EN
127
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