MT41J256M4 Datasheet, PDF (111/181 Pages) Micon Design Technology Corporation – 1Gb: x4, x8, x16 DDR3 SDRAM

1Gb: x4, x8, x16 DDR3 SDRAM
Operations
Table 68: Burst Order
Burst
Length
4 chop
8
READ/
WRITE
READ
WRITE
READ
WRITE
Starting Column
Address
(A[2, 1, 0])
000
001
010
011
100
101
110
111
0VV
1VV
000
001
010
011
100
101
110
111
VVV
Burst Type = Sequential
(Decimal)
0, 1, 2, 3, Z, Z, Z, Z
1, 2, 3, 0, Z, Z, Z, Z
2, 3, 0, 1, Z, Z, Z, Z
3, 0, 1, 2, Z, Z, Z, Z
4, 5, 6, 7, Z, Z, Z, Z
5, 6, 7, 4, Z, Z, Z, Z
6, 7, 4, 5, Z, Z, Z, Z
7, 4, 5, 6, Z, Z, Z, Z
0, 1, 2, 3, X, X, X, X
4, 5, 6, 7, X, X, X, X
0, 1, 2, 3, 4, 5, 6, 7
1, 2, 3, 0, 5, 6, 7, 4
2, 3, 0, 1, 6, 7, 4, 5
3, 0, 1, 2, 7, 4, 5, 6
4, 5, 6, 7, 0, 1, 2, 3
5, 6, 7, 4, 1, 2, 3, 0
6, 7, 4, 5, 2, 3, 0, 1
7, 4, 5, 6, 3, 0, 1, 2
0, 1, 2, 3, 4, 5, 6, 7
Burst Type = Interleaved
(Decimal)
0, 1, 2, 3, Z, Z, Z, Z
1, 0, 3, 2, Z, Z, Z, Z
2, 3, 0, 1, Z, Z, Z, Z
3, 2, 1, 0, Z, Z, Z, Z
4, 5, 6, 7, Z, Z, Z, Z
5, 4, 7, 6, Z, Z, Z, Z
6, 7, 4, 5, Z, Z, Z, Z
7, 6, 5, 4, Z, Z, Z, Z
0, 1, 2, 3, X, X, X, X
4, 5, 6, 7, X, X, X, X
0, 1, 2, 3, 4, 5, 6, 7
1, 0, 3, 2, 5, 4, 7, 6
2, 3, 0, 1, 6, 7, 4, 5
3, 2, 1, 0, 7, 6, 5, 4
4, 5, 6, 7, 0, 1, 2, 3
5, 4, 7, 6, 1, 0, 3, 2
6, 7, 4, 5, 2, 3, 0, 1
7, 6, 5, 4, 3, 2, 1, 0
0, 1, 2, 3, 4, 5, 6, 7
Notes
1, 2
1, 2
1, 2
1, 2
1, 2
1, 2
1, 2
1, 2
1, 3, 4
1, 3, 4
1
1
1
1
1
1
1
1
1, 3
Notes:
1. Internal READ and WRITE operations start at the same point in time for BC4 as they do for
BL8.
2. Z = Data and strobe output drivers are in tri-state.
3. V = A valid logic level (0 or 1), but the respective input buffer ignores level-on input pins.
4. X = “Don’t Care.”
DLL RESET
DLL RESET is defined by MR0[8] (see Figure 54 on page 110). Programming MR0[8] to
“1” activates the DLL RESET function. MR0[8] is self-clearing, meaning it returns to a
value of “0” after the DLL RESET function has been initiated.
Anytime the DLL RESET function is initiated, CKE must be HIGH and the clock held
stable for 512 (^tDLLK) clock cycles before a READ command can be issued. This is to
allow time for the internal clock to be synchronized with the external clock. Failing to
wait for synchronization to occur may result in invalid output timing specifications,
such as ^tDQSCK timings.
Write Recovery
WRITE recovery time is defined by MR0[11:9] (see Figure 54 on page 110). Write
recovery values of 5, 6, 7, 8, 10, or 12 may be used by programming MR0[11:9]. The user
is required to program the correct value of write recovery and is calculated by dividing
t_{WR (ns) by} t_{CK (ns) and rounding up a noninteger value to the next integer: WR (cycles)}
= roundup (^tWR [ns]/^tCK [ns]).
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1Gb_DDR3_4.fm - Rev. D 8/1/08 EN
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