MT41J256M4 Datasheet, PDF (1/181 Pages) Micon Design Technology Corporation – 1Gb: x4, x8, x16 DDR3 SDRAM

DDR3 SDRAM
MT41J256M4 – 32 Meg x 4 x 8 Banks
MT41J128M8 – 16 Meg x 8 x 8 Banks
MT41J64M16 – 8 Meg x 16 x 8 Banks
1Gb: x4, x8, x16 DDR3 SDRAM
Features
Features
• VDD = VDDQ = +1.5V ±0.075V
• 1.5V center-terminated push/pull I/O
• Differential bidirectional data strobe
• 8n-bit prefetch architecture
• Differential clock inputs (CK, CK#)
• 8 internal banks
• Nominal and dynamic on-die termination (ODT) for
data, strobe, and mask signals
• CAS (READ) latency (CL): 5, 6, 7, 8, 9, 10, or 11
• POSTED CAS ADDITIVE latency (AL): 0, CL - 1, CL - 2
• CAS (WRITE) latency (CWL): 5, 6, 7, 8, based on ^tCK
• Fixed burst length (BL) of 8 and burst chop (BC) of 4
(via the mode register set [MRS])
• Selectable BC4 or BL8 on-the-fly (OTF)
• Self refresh mode
• T_C of 0^oC to 95^oC
– 64ms, 8,192 cycle refresh at 0^oC to 85^oC
– 32ms at 85^oC to 95^oC
• Clock frequency range of 300–800 MHz
• Self refresh temperature (SRT)
• Automatic self refresh (ASR)
• Write leveling
• Multipurpose register
• Output driver calibration
Options
Marking
• Configuration
– 256 Meg x 4
256M4
– 128 Meg x 8
128M8
– 64 Meg x 16
64M16
• FBGA package (Pb-free) - x4, x8
– 78-ball FBGA (8mm x 11.5mm) Rev. F
JP
– 78-ball FBGA (9mm x 11.5mm) Rev. D
HX
– 86-ball FBGA (9mm x 15.5mm) Rev. B
BY
• FBGA package (Pb-free) - x16
– 96-ball FBGA (9mm x 15.5mm) Rev. B
LA
• Timing - cycle time
– 1.25ns @ CL = 11 (DDR3-1600)
-125
– 1.25ns @ CL = 10 (DDR3-1600)
-125E
– 1.25ns @ CL = 9 (DDR3-1600)
-125F
– 1.5ns @ CL = 10 (DDR3-1333)
-15
– 1.5ns @ CL = 9 (DDR3-1333)
-15E
– 1.5ns @ CL = 8 (DDR3-1333)
-15F
– 1.87ns @ CL = 8 (DDR3-1066)
-187
– 1.87ns @ CL = 7 (DDR3-1066)
-187E
– 2.5ns @ CL = 6 (DDR3-800)
-25
– 2.5ns @ CL = 5 (DDR3-800)
-25E
• Revision
:B/:D/:F
Table 1: Key Timing Parameters
Speed Grade
-125
-125E
-125F
-15
-15E
-15F
-187
-187E
-25
-25E
Data Rate (MT/s)
1600
1600
1600
1333
1333
1333
1066
1066
800
800
Target ^tRCD-^tRP-CL
11-11-11
10-10-10
9-9-9
10-10-10
9-9-9
8-8-8
8-8-8
7-7-7
6-6-6
5-5-5
t_{RCD (ns)}
13.75
12.5
11.25
15
13.5
12
15
13.1
15
12.5
t_{RP (ns)}
13.75
12.5
11.25
15
13.5
12
15
13.1
15
12.5
CL (ns)
13.75
12.5
11.25
15
13.5
12
15
13.1
15
12.5
PDF: 09005aef826aa906/Source: 09005aef82a357c3
1Gb_DDR3_D1 .fm - Rev. D 8/1/08 EN
1
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Products and specifications discussed herein are subject to change by Micron without notice.