MT41J256M4 Datasheet, PDF (166/181 Pages) Micon Design Technology Corporation – 1Gb: x4, x8, x16 DDR3 SDRAM

1Gb: x4, x8, x16 DDR3 SDRAM
On-Die Termination (ODT)
Figure 114: Dynamic ODT: ODT Pin Asserted with WRITE Command for 6 Clock Cycles, BC4
CK#
CK
Command
T0
NOP
Address
T1
WRS4
Valid
T2
T3
T4
NOP
NOP
ODTLCNW
NOP
ODTH4
T5
NOP
T6
NOP
T7
NOP
T8
NOP
T9
NOP
ODTL off
T10
NOP
T11
NOP
ODT
RTT
DQS, DQS#
DQ
ODTL on
tAD_{C (MAX)}
RTT_WR
tAON _(MIN)
ODTLCWN4
tAD_{C (MIN)}
RTT_NOM
tAD_{C (MAX)}
tAOF _(MIN)
tAOF _(MAX)
DI
DI DI DI
n n+1 n+2 n+3
WL
Transitioning
Don’t Care
Notes:
1. Via MRS or OTF. AL = 0, CWL = 5. RTT_NOM and RTT_WR are enabled.
2. ODTH4 is defined from ODT registered HIGH to ODT registered LOW, so in this example,
ODTH4 is satisfied. ODT registered LOW at T5 is also legal.
Figure 115: Dynamic ODT: ODT Pin Asserted with WRITE Command for 4 Clock Cycles, BC4
CK#
CK
Command
T0
NOP
Address
ODT
RTT
DQS, DQS#
DQ
T1
WRS4
Valid
T2
T3
T4
NOP
NOP
ODTLCNW
NOP
ODTH4
T5
NOP
T6
NOP
T7
NOP
ODTL off
ODTL on
tAD_{C (MAX)}
tAON _(MIN)
ODTLCWN4
RTRT_TTW_RWR
T8
NOP
T9
NOP
T10
NOP
tAOF _(MIN)
tAOF _(MAX)
T11
NOP
WL
DI
DI DI DI
n n+1 n+2 n+3
Transitioning
Don’t Care
Notes:
1. Via MRS or OTF. AL = 0, CWL = 5. RTT_NOM can be either enabled or disabled. If disabled,
ODT can remain HIGH. RTT_WR is enabled.
2. In this example ODTH4 = 4 is satisfied exactly.
PDF: 09005aef826aa906/Source: 09005aef82a357c3
1Gb_DDR3_5.fm - Rev. D 8/1/08 EN
166
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