MT41J256M4 Datasheet, PDF (35/181 Pages) Micon Design Technology Corporation – 1Gb: x4, x8, x16 DDR3 SDRAM

1Gb: x4, x8, x16 DDR3 SDRAM
Electrical Specifications – IDD Specifications and Conditions
Table 15: IDD Measurement Conditions for IDD4R, IDD4W
IDD Test
IDD4R: Burst Read Operating Current IDD4W: Burst Write Operating Current Notes
Timing diagram example
CKE
External clock
t_CK
t_RC
t_RAS
t_RCD
t_RRD
t_RC
CL
AL
CS#
Figure 16 on page 36
HIGH
On
t_{CK (MIN) IDD}
n/a
n/a
n/a
n/a
n/a
CL IDD
0
HIGH between valid commands
–
HIGH
On
t_{CK (MIN) IDD}
n/a
n/a
n/a
n/a
n/a
CL IDD
0
HIGH between valid commands
Command inputs
Switching;
READ command/pattern:
R0DDDR1DDDR2DDDR3DDDR4 . . .
Rx = READ from bank x
Switching;
1
WRITE command/pattern:
W0DDDW1DDDW2DDDW3DDDW4 . . .
Wx = WRITE to bank x
Row/column addresses
Column addresses switching;
Column addresses switching;
1
Address input A10 must always be LOW Address input A10 must always be LOW
Bank addresses
Bank address looping (0-to-1-to-2-to-3 . . . ) Bank address looping (0-to-1-to-2-to-3 . . . )
Data I/O
Seamless read data burst (BL8): Output Seamless write data burst (BL8): Input data 2
data switches after every clock cycle, which switches after every clock cycle, which
means that read data is stable during
means that write data is stable during
falling DQS
falling DQS
Output buffer DQ, DQS
Off
Off
ODT
Disabled
Disabled
Burst length
8 fixed (via MR0)
8 fixed (via MR0)
Active banks
All
All
Idle banks
None
None
Special notes
n/a
DM always LOW
Notes: 1. For further definition of input switching, see Table 10 on page 29.
2. For further definition of data switching, see Table 11 on page 29.
PDF: 09005aef826aa906/Source: 09005aef82a357c3
1Gb_DDR3_D2.fm - Rev. D 8/1/08 EN
35
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2006 Micron Technology, Inc. All rights reserved.