MT41J256M4 Datasheet, PDF (125/181 Pages) Micon Design Technology Corporation – 1Gb: x4, x8, x16 DDR3 SDRAM

Figure 65: MPR System Read Calibration with BC4: Upper Nibble, Then Lower Nibble
CK#
CK
Command
T0
PREA
Ta
Tb
Tc0
Tc1
MRS
READ1
READ1
NOP
tRF
tMOD
t_CCD
Bank address
3
Valid
Valid
A[1:0]
0
02
02
A2
1
13
04
A[9:3]
00
Valid
Valid
A10/AP
1
0
Valid
Valid
A11
0
Valid
Valid
A12/BC#
0
Valid¹
Valid¹
A[15:13]
0
Valid
Valid
RL
DQS, DQS#
DQ
Tc2
Tc3
NOP
NOP
RL
Tc4
Tc5
NOP
NOP
Tc6
Tc7
Tc8
Tc9
Tc10
Td
NOP
NOP
MRS
NOP
NOP
Valid
tMPRR
tMOD
3
Valid
0
00
0
0
0
0
Notes:
1. READ with BC4 either by MRS or OTF.
2. Memory controller must drive 0 on A[1:0].
3. A2 = 1 selects upper 4 nibble bits 4 . . . 7.
4. A2 = 0 selects lower 4 nibble bits 0 . . . 3.
Indicates A Break in
Time Scale
Don’t Care