MAX1415 Datasheet, PDF (8/36 Pages) Maxim Integrated Products – 16-Bit, Low-Power, 2-Channel, Sigma-Delta ADCs

16-Bit, Low-Power, 2-Channel,
Sigma-Delta ADCs
ELECTRICAL CHARACTERISTICS—MAX1416 (continued)
(V_DD = 5V, GND = 0, V_REF+ = 2.5V, V_REF- = GND, f_CLKIN = 2.4576MHz, CLKDIV bit = 0, C_REF+ to GND = 0.1µF, C_REF- to GND =
0.1µF, T_A = T_MIN to T_MAX, unless otherwise noted.)
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX UNITS
Unbuffered, f_CLKIN = 1MHz, gain = 1 to 128
0.45
Power-Supply Current (Note 12)
Buffered, f_CLKIN = 1MHz, gain = 1 to 128
Unbuffered,
Gain = 1 to 4
I_DD
f_CLKIN = 2.4576MHz
Gain = 8 to 128
0.78
0.6
mA
0.6
Buffered,
Gain = 1 to 4
0.95
f_CLKIN = 2.4576MHz
Gain = 8 to 128
1.1
Power-down mode (Note 13)
16
µA
Power-Supply Rejection Ratio
PSRR
EXTERNAL-CLOCK SPECIFICATIONS
V_DD = 4.75V to 5.25V
(Note 14)
dB
CLKIN Frequency
Duty Cycle
f_CLKIN (Note 15)
400
2500 kHz
40
60
%
INTERNAL-CLOCK TIMING SPECIFICATIONS
MAX1416AE__,
f_CLK = 1MHz (CLK = 0)
or 2.4576MHz (CLK = 1)
T_A = -40°C to
+85°C
±4
Internal-Clock Frequency
f_CLK
MAX1416C__,
f_CLK = 1MHz (CLK = 0)
or 2.4576MHz (CLK = 1)
T_A = 0°C to
+70°C
±4
%
Typical Conversion-Time
Variation
∆t_CONV
MAX1416E__,
T_A = -40°C to 0°C
f_CLK = 1MHz (CLK = 0)
or 2.4576MHz (CLK = 1) TA= 0°C to +85°C
t_CONV = 1/ODR,
CLK = 0 (1MHz), INTCLK = 1
±7
±4
±0.5
%
TIMING CHARACTERISTICS—MAX1416
(Note 16) (Figures 8, 9)
PARAMETER
SYMBOL
DRDY High Time
Reset Pulse-Width Low
DRDY Fall to CS Fall Setup Time
t₁
CS Fall to SCLK Rise Setup Time
t₂
SCLK Fall to DOUT Valid Delay
t₃
SCLK Pulse-Width High
t₄
SCLK Pulse-Width Low
t₅
CS Rise to SCLK Rise Hold Time
t₆
Bus Relinquish Time After SCLK
Rising Edge
t₇
SCLK Fall to DRDY Rise Delay
t₈
CONDITIONS
MIN
500 /
f_CLKIN
100
0
120
0
100
100
0
TYP
MAX
80
60
100
UNITS
s
ns
ns
ns
ns
ns
ns
ns
ns
ns
8 _______________________________________________________________________________________